1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and 5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains 6 * cpu specific common code for 85xx/86xx processors. 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <config.h> 27 #include <common.h> 28 #include <command.h> 29 #include <tsec.h> 30 #include <fm_eth.h> 31 #include <netdev.h> 32 #include <asm/cache.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static struct cpu_type cpu_type_list[] = { 38 #if defined(CONFIG_MPC85xx) 39 CPU_TYPE_ENTRY(8533, 8533, 1), 40 CPU_TYPE_ENTRY(8535, 8535, 1), 41 CPU_TYPE_ENTRY(8536, 8536, 1), 42 CPU_TYPE_ENTRY(8540, 8540, 1), 43 CPU_TYPE_ENTRY(8541, 8541, 1), 44 CPU_TYPE_ENTRY(8543, 8543, 1), 45 CPU_TYPE_ENTRY(8544, 8544, 1), 46 CPU_TYPE_ENTRY(8545, 8545, 1), 47 CPU_TYPE_ENTRY(8547, 8547, 1), 48 CPU_TYPE_ENTRY(8548, 8548, 1), 49 CPU_TYPE_ENTRY(8555, 8555, 1), 50 CPU_TYPE_ENTRY(8560, 8560, 1), 51 CPU_TYPE_ENTRY(8567, 8567, 1), 52 CPU_TYPE_ENTRY(8568, 8568, 1), 53 CPU_TYPE_ENTRY(8569, 8569, 1), 54 CPU_TYPE_ENTRY(8572, 8572, 2), 55 CPU_TYPE_ENTRY(P1010, P1010, 1), 56 CPU_TYPE_ENTRY(P1011, P1011, 1), 57 CPU_TYPE_ENTRY(P1012, P1012, 1), 58 CPU_TYPE_ENTRY(P1013, P1013, 1), 59 CPU_TYPE_ENTRY(P1014, P1014, 1), 60 CPU_TYPE_ENTRY(P1017, P1017, 1), 61 CPU_TYPE_ENTRY(P1020, P1020, 2), 62 CPU_TYPE_ENTRY(P1021, P1021, 2), 63 CPU_TYPE_ENTRY(P1022, P1022, 2), 64 CPU_TYPE_ENTRY(P1023, P1023, 2), 65 CPU_TYPE_ENTRY(P1024, P1024, 2), 66 CPU_TYPE_ENTRY(P1025, P1025, 2), 67 CPU_TYPE_ENTRY(P2010, P2010, 1), 68 CPU_TYPE_ENTRY(P2020, P2020, 2), 69 CPU_TYPE_ENTRY(P2040, P2040, 4), 70 CPU_TYPE_ENTRY(P2041, P2041, 4), 71 CPU_TYPE_ENTRY(P3041, P3041, 4), 72 CPU_TYPE_ENTRY(P4040, P4040, 4), 73 CPU_TYPE_ENTRY(P4080, P4080, 8), 74 CPU_TYPE_ENTRY(P5010, P5010, 1), 75 CPU_TYPE_ENTRY(P5020, P5020, 2), 76 CPU_TYPE_ENTRY(P5021, P5021, 2), 77 CPU_TYPE_ENTRY(P5040, P5040, 4), 78 CPU_TYPE_ENTRY(T4240, T4240, 0), 79 CPU_TYPE_ENTRY(T4120, T4120, 0), 80 CPU_TYPE_ENTRY(T4160, T4160, 0), 81 CPU_TYPE_ENTRY(B4860, B4860, 0), 82 CPU_TYPE_ENTRY(G4860, G4860, 0), 83 CPU_TYPE_ENTRY(G4060, G4060, 0), 84 CPU_TYPE_ENTRY(B4440, B4440, 0), 85 CPU_TYPE_ENTRY(G4440, G4440, 0), 86 CPU_TYPE_ENTRY(B4420, B4420, 0), 87 CPU_TYPE_ENTRY(B4220, B4220, 0), 88 CPU_TYPE_ENTRY(T1040, T1040, 0), 89 CPU_TYPE_ENTRY(T1041, T1041, 0), 90 CPU_TYPE_ENTRY(T1042, T1042, 0), 91 CPU_TYPE_ENTRY(T1020, T1020, 0), 92 CPU_TYPE_ENTRY(T1021, T1021, 0), 93 CPU_TYPE_ENTRY(T1022, T1022, 0), 94 CPU_TYPE_ENTRY(BSC9130, 9130, 1), 95 CPU_TYPE_ENTRY(BSC9131, 9131, 1), 96 CPU_TYPE_ENTRY(BSC9132, 9132, 2), 97 CPU_TYPE_ENTRY(BSC9232, 9232, 2), 98 #elif defined(CONFIG_MPC86xx) 99 CPU_TYPE_ENTRY(8610, 8610, 1), 100 CPU_TYPE_ENTRY(8641, 8641, 2), 101 CPU_TYPE_ENTRY(8641D, 8641D, 2), 102 #endif 103 }; 104 105 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 106 static inline u32 init_type(u32 cluster, int init_id) 107 { 108 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 109 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 110 u32 type = in_be32(&gur->tp_ityp[idx]); 111 112 if (type & TP_ITYP_AV) 113 return type; 114 115 return 0; 116 } 117 118 u32 compute_ppc_cpumask(void) 119 { 120 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 121 int i = 0, count = 0; 122 u32 cluster, type, mask = 0; 123 124 do { 125 int j; 126 cluster = in_be32(&gur->tp_cluster[i].lower); 127 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 128 type = init_type(cluster, j); 129 if (type) { 130 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 131 mask |= 1 << count; 132 count++; 133 } 134 } 135 i++; 136 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 137 138 return mask; 139 } 140 141 int fsl_qoriq_core_to_cluster(unsigned int core) 142 { 143 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 144 int i = 0, count = 0; 145 u32 cluster; 146 147 do { 148 int j; 149 cluster = in_be32(&gur->tp_cluster[i].lower); 150 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 151 if (init_type(cluster, j)) { 152 if (count == core) 153 return i; 154 count++; 155 } 156 } 157 i++; 158 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 159 160 return -1; /* cannot identify the cluster */ 161 } 162 163 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 164 /* 165 * Before chassis genenration 2, the cpumask should be hard-coded. 166 * In case of cpu type unknown or cpumask unset, use 1 as fail save. 167 */ 168 #define compute_ppc_cpumask() 1 169 #define fsl_qoriq_core_to_cluster(x) x 170 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 171 172 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); 173 174 struct cpu_type *identify_cpu(u32 ver) 175 { 176 int i; 177 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { 178 if (cpu_type_list[i].soc_ver == ver) 179 return &cpu_type_list[i]; 180 } 181 return &cpu_type_unknown; 182 } 183 184 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 185 #define MPC8xxx_PICFRR_NCPU_SHIFT 8 186 187 /* 188 * Return a 32-bit mask indicating which cores are present on this SOC. 189 */ 190 u32 cpu_mask(void) 191 { 192 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; 193 struct cpu_type *cpu = gd->arch.cpu; 194 195 /* better to query feature reporting register than just assume 1 */ 196 if (cpu == &cpu_type_unknown) 197 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> 198 MPC8xxx_PICFRR_NCPU_SHIFT) + 1; 199 200 if (cpu->num_cores == 0) 201 return compute_ppc_cpumask(); 202 203 return cpu->mask; 204 } 205 206 /* 207 * Return the number of cores on this SOC. 208 */ 209 int cpu_numcores(void) 210 { 211 struct cpu_type *cpu = gd->arch.cpu; 212 213 /* 214 * Report # of cores in terms of the cpu_mask if we haven't 215 * figured out how many there are yet 216 */ 217 if (cpu->num_cores == 0) 218 return hweight32(cpu_mask()); 219 220 return cpu->num_cores; 221 } 222 223 /* 224 * Check if the given core ID is valid 225 * 226 * Returns zero if it isn't, 1 if it is. 227 */ 228 int is_core_valid(unsigned int core) 229 { 230 return !!((1 << core) & cpu_mask()); 231 } 232 233 int probecpu (void) 234 { 235 uint svr; 236 uint ver; 237 238 svr = get_svr(); 239 ver = SVR_SOC_VER(svr); 240 241 gd->arch.cpu = identify_cpu(ver); 242 243 return 0; 244 } 245 246 /* Once in memory, compute mask & # cores once and save them off */ 247 int fixup_cpu(void) 248 { 249 struct cpu_type *cpu = gd->arch.cpu; 250 251 if (cpu->num_cores == 0) { 252 cpu->mask = cpu_mask(); 253 cpu->num_cores = cpu_numcores(); 254 } 255 256 return 0; 257 } 258 259 /* 260 * Initializes on-chip ethernet controllers. 261 * to override, implement board_eth_init() 262 */ 263 int cpu_eth_init(bd_t *bis) 264 { 265 #if defined(CONFIG_ETHER_ON_FCC) 266 fec_initialize(bis); 267 #endif 268 269 #if defined(CONFIG_UEC_ETH) 270 uec_standard_init(bis); 271 #endif 272 273 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) 274 tsec_standard_init(bis); 275 #endif 276 277 #ifdef CONFIG_FMAN_ENET 278 fm_standard_init(bis); 279 #endif 280 return 0; 281 } 282