1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and 5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains 6 * cpu specific common code for 85xx/86xx processors. 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <tsec.h> 14 #include <fm_eth.h> 15 #include <netdev.h> 16 #include <asm/cache.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static struct cpu_type cpu_type_list[] = { 22 #if defined(CONFIG_MPC85xx) 23 CPU_TYPE_ENTRY(8533, 8533, 1), 24 CPU_TYPE_ENTRY(8535, 8535, 1), 25 CPU_TYPE_ENTRY(8536, 8536, 1), 26 CPU_TYPE_ENTRY(8540, 8540, 1), 27 CPU_TYPE_ENTRY(8541, 8541, 1), 28 CPU_TYPE_ENTRY(8543, 8543, 1), 29 CPU_TYPE_ENTRY(8544, 8544, 1), 30 CPU_TYPE_ENTRY(8545, 8545, 1), 31 CPU_TYPE_ENTRY(8547, 8547, 1), 32 CPU_TYPE_ENTRY(8548, 8548, 1), 33 CPU_TYPE_ENTRY(8555, 8555, 1), 34 CPU_TYPE_ENTRY(8560, 8560, 1), 35 CPU_TYPE_ENTRY(8567, 8567, 1), 36 CPU_TYPE_ENTRY(8568, 8568, 1), 37 CPU_TYPE_ENTRY(8569, 8569, 1), 38 CPU_TYPE_ENTRY(8572, 8572, 2), 39 CPU_TYPE_ENTRY(P1010, P1010, 1), 40 CPU_TYPE_ENTRY(P1011, P1011, 1), 41 CPU_TYPE_ENTRY(P1012, P1012, 1), 42 CPU_TYPE_ENTRY(P1013, P1013, 1), 43 CPU_TYPE_ENTRY(P1014, P1014, 1), 44 CPU_TYPE_ENTRY(P1017, P1017, 1), 45 CPU_TYPE_ENTRY(P1020, P1020, 2), 46 CPU_TYPE_ENTRY(P1021, P1021, 2), 47 CPU_TYPE_ENTRY(P1022, P1022, 2), 48 CPU_TYPE_ENTRY(P1023, P1023, 2), 49 CPU_TYPE_ENTRY(P1024, P1024, 2), 50 CPU_TYPE_ENTRY(P1025, P1025, 2), 51 CPU_TYPE_ENTRY(P2010, P2010, 1), 52 CPU_TYPE_ENTRY(P2020, P2020, 2), 53 CPU_TYPE_ENTRY(P2040, P2040, 4), 54 CPU_TYPE_ENTRY(P2041, P2041, 4), 55 CPU_TYPE_ENTRY(P3041, P3041, 4), 56 CPU_TYPE_ENTRY(P4040, P4040, 4), 57 CPU_TYPE_ENTRY(P4080, P4080, 8), 58 CPU_TYPE_ENTRY(P5010, P5010, 1), 59 CPU_TYPE_ENTRY(P5020, P5020, 2), 60 CPU_TYPE_ENTRY(P5021, P5021, 2), 61 CPU_TYPE_ENTRY(P5040, P5040, 4), 62 CPU_TYPE_ENTRY(T4240, T4240, 0), 63 CPU_TYPE_ENTRY(T4120, T4120, 0), 64 CPU_TYPE_ENTRY(T4160, T4160, 0), 65 CPU_TYPE_ENTRY(T4080, T4080, 4), 66 CPU_TYPE_ENTRY(B4860, B4860, 0), 67 CPU_TYPE_ENTRY(G4860, G4860, 0), 68 CPU_TYPE_ENTRY(B4440, B4440, 0), 69 CPU_TYPE_ENTRY(B4460, B4460, 0), 70 CPU_TYPE_ENTRY(G4440, G4440, 0), 71 CPU_TYPE_ENTRY(B4420, B4420, 0), 72 CPU_TYPE_ENTRY(B4220, B4220, 0), 73 CPU_TYPE_ENTRY(T1040, T1040, 0), 74 CPU_TYPE_ENTRY(T1041, T1041, 0), 75 CPU_TYPE_ENTRY(T1042, T1042, 0), 76 CPU_TYPE_ENTRY(T1020, T1020, 0), 77 CPU_TYPE_ENTRY(T1021, T1021, 0), 78 CPU_TYPE_ENTRY(T1022, T1022, 0), 79 CPU_TYPE_ENTRY(T1024, T1024, 0), 80 CPU_TYPE_ENTRY(T1023, T1023, 0), 81 CPU_TYPE_ENTRY(T1014, T1014, 0), 82 CPU_TYPE_ENTRY(T1013, T1013, 0), 83 CPU_TYPE_ENTRY(T2080, T2080, 0), 84 CPU_TYPE_ENTRY(T2081, T2081, 0), 85 CPU_TYPE_ENTRY(BSC9130, 9130, 1), 86 CPU_TYPE_ENTRY(BSC9131, 9131, 1), 87 CPU_TYPE_ENTRY(BSC9132, 9132, 2), 88 CPU_TYPE_ENTRY(BSC9232, 9232, 2), 89 CPU_TYPE_ENTRY(C291, C291, 1), 90 CPU_TYPE_ENTRY(C292, C292, 1), 91 CPU_TYPE_ENTRY(C293, C293, 1), 92 #elif defined(CONFIG_MPC86xx) 93 CPU_TYPE_ENTRY(8610, 8610, 1), 94 CPU_TYPE_ENTRY(8641, 8641, 2), 95 CPU_TYPE_ENTRY(8641D, 8641D, 2), 96 #endif 97 }; 98 99 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 100 static inline u32 init_type(u32 cluster, int init_id) 101 { 102 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 103 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 104 u32 type = in_be32(&gur->tp_ityp[idx]); 105 106 if (type & TP_ITYP_AV) 107 return type; 108 109 return 0; 110 } 111 112 u32 compute_ppc_cpumask(void) 113 { 114 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 115 int i = 0, count = 0; 116 u32 cluster, type, mask = 0; 117 118 do { 119 int j; 120 cluster = in_be32(&gur->tp_cluster[i].lower); 121 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 122 type = init_type(cluster, j); 123 if (type) { 124 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 125 mask |= 1 << count; 126 count++; 127 } 128 } 129 i++; 130 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 131 132 return mask; 133 } 134 135 int fsl_qoriq_core_to_cluster(unsigned int core) 136 { 137 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 138 int i = 0, count = 0; 139 u32 cluster; 140 141 do { 142 int j; 143 cluster = in_be32(&gur->tp_cluster[i].lower); 144 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 145 if (init_type(cluster, j)) { 146 if (count == core) 147 return i; 148 count++; 149 } 150 } 151 i++; 152 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 153 154 return -1; /* cannot identify the cluster */ 155 } 156 157 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 158 /* 159 * Before chassis genenration 2, the cpumask should be hard-coded. 160 * In case of cpu type unknown or cpumask unset, use 1 as fail save. 161 */ 162 #define compute_ppc_cpumask() 1 163 #define fsl_qoriq_core_to_cluster(x) x 164 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 165 166 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); 167 168 struct cpu_type *identify_cpu(u32 ver) 169 { 170 int i; 171 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { 172 if (cpu_type_list[i].soc_ver == ver) 173 return &cpu_type_list[i]; 174 } 175 return &cpu_type_unknown; 176 } 177 178 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 179 #define MPC8xxx_PICFRR_NCPU_SHIFT 8 180 181 /* 182 * Return a 32-bit mask indicating which cores are present on this SOC. 183 */ 184 __weak u32 cpu_mask(void) 185 { 186 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; 187 struct cpu_type *cpu = gd->arch.cpu; 188 189 /* better to query feature reporting register than just assume 1 */ 190 if (cpu == &cpu_type_unknown) 191 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> 192 MPC8xxx_PICFRR_NCPU_SHIFT) + 1; 193 194 if (cpu->num_cores == 0) 195 return compute_ppc_cpumask(); 196 197 return cpu->mask; 198 } 199 200 /* 201 * Return the number of cores on this SOC. 202 */ 203 __weak int cpu_numcores(void) 204 { 205 struct cpu_type *cpu = gd->arch.cpu; 206 207 /* 208 * Report # of cores in terms of the cpu_mask if we haven't 209 * figured out how many there are yet 210 */ 211 if (cpu->num_cores == 0) 212 return hweight32(cpu_mask()); 213 214 return cpu->num_cores; 215 } 216 217 /* 218 * Check if the given core ID is valid 219 * 220 * Returns zero if it isn't, 1 if it is. 221 */ 222 int is_core_valid(unsigned int core) 223 { 224 return !!((1 << core) & cpu_mask()); 225 } 226 227 int probecpu (void) 228 { 229 uint svr; 230 uint ver; 231 232 svr = get_svr(); 233 ver = SVR_SOC_VER(svr); 234 235 gd->arch.cpu = identify_cpu(ver); 236 237 return 0; 238 } 239 240 /* Once in memory, compute mask & # cores once and save them off */ 241 int fixup_cpu(void) 242 { 243 struct cpu_type *cpu = gd->arch.cpu; 244 245 if (cpu->num_cores == 0) { 246 cpu->mask = cpu_mask(); 247 cpu->num_cores = cpu_numcores(); 248 } 249 250 return 0; 251 } 252 253 /* 254 * Initializes on-chip ethernet controllers. 255 * to override, implement board_eth_init() 256 */ 257 int cpu_eth_init(bd_t *bis) 258 { 259 #if defined(CONFIG_ETHER_ON_FCC) 260 fec_initialize(bis); 261 #endif 262 263 #if defined(CONFIG_UEC_ETH) 264 uec_standard_init(bis); 265 #endif 266 267 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) 268 tsec_standard_init(bis); 269 #endif 270 271 #ifdef CONFIG_FMAN_ENET 272 fm_standard_init(bis); 273 #endif 274 return 0; 275 } 276