1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and 5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains 6 * cpu specific common code for 85xx/86xx processors. 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <tsec.h> 14 #include <fm_eth.h> 15 #include <netdev.h> 16 #include <asm/cache.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static struct cpu_type cpu_type_list[] = { 22 #if defined(CONFIG_MPC85xx) 23 CPU_TYPE_ENTRY(8533, 8533, 1), 24 CPU_TYPE_ENTRY(8535, 8535, 1), 25 CPU_TYPE_ENTRY(8536, 8536, 1), 26 CPU_TYPE_ENTRY(8540, 8540, 1), 27 CPU_TYPE_ENTRY(8541, 8541, 1), 28 CPU_TYPE_ENTRY(8543, 8543, 1), 29 CPU_TYPE_ENTRY(8544, 8544, 1), 30 CPU_TYPE_ENTRY(8545, 8545, 1), 31 CPU_TYPE_ENTRY(8547, 8547, 1), 32 CPU_TYPE_ENTRY(8548, 8548, 1), 33 CPU_TYPE_ENTRY(8555, 8555, 1), 34 CPU_TYPE_ENTRY(8560, 8560, 1), 35 CPU_TYPE_ENTRY(8567, 8567, 1), 36 CPU_TYPE_ENTRY(8568, 8568, 1), 37 CPU_TYPE_ENTRY(8569, 8569, 1), 38 CPU_TYPE_ENTRY(8572, 8572, 2), 39 CPU_TYPE_ENTRY(P1010, P1010, 1), 40 CPU_TYPE_ENTRY(P1011, P1011, 1), 41 CPU_TYPE_ENTRY(P1012, P1012, 1), 42 CPU_TYPE_ENTRY(P1013, P1013, 1), 43 CPU_TYPE_ENTRY(P1014, P1014, 1), 44 CPU_TYPE_ENTRY(P1017, P1017, 1), 45 CPU_TYPE_ENTRY(P1020, P1020, 2), 46 CPU_TYPE_ENTRY(P1021, P1021, 2), 47 CPU_TYPE_ENTRY(P1022, P1022, 2), 48 CPU_TYPE_ENTRY(P1023, P1023, 2), 49 CPU_TYPE_ENTRY(P1024, P1024, 2), 50 CPU_TYPE_ENTRY(P1025, P1025, 2), 51 CPU_TYPE_ENTRY(P2010, P2010, 1), 52 CPU_TYPE_ENTRY(P2020, P2020, 2), 53 CPU_TYPE_ENTRY(P2040, P2040, 4), 54 CPU_TYPE_ENTRY(P2041, P2041, 4), 55 CPU_TYPE_ENTRY(P3041, P3041, 4), 56 CPU_TYPE_ENTRY(P4040, P4040, 4), 57 CPU_TYPE_ENTRY(P4080, P4080, 8), 58 CPU_TYPE_ENTRY(P5010, P5010, 1), 59 CPU_TYPE_ENTRY(P5020, P5020, 2), 60 CPU_TYPE_ENTRY(P5021, P5021, 2), 61 CPU_TYPE_ENTRY(P5040, P5040, 4), 62 CPU_TYPE_ENTRY(T4240, T4240, 0), 63 CPU_TYPE_ENTRY(T4120, T4120, 0), 64 CPU_TYPE_ENTRY(T4160, T4160, 0), 65 CPU_TYPE_ENTRY(B4860, B4860, 0), 66 CPU_TYPE_ENTRY(G4860, G4860, 0), 67 CPU_TYPE_ENTRY(G4060, G4060, 0), 68 CPU_TYPE_ENTRY(B4440, B4440, 0), 69 CPU_TYPE_ENTRY(G4440, G4440, 0), 70 CPU_TYPE_ENTRY(B4420, B4420, 0), 71 CPU_TYPE_ENTRY(B4220, B4220, 0), 72 CPU_TYPE_ENTRY(T1040, T1040, 0), 73 CPU_TYPE_ENTRY(T1041, T1041, 0), 74 CPU_TYPE_ENTRY(T1042, T1042, 0), 75 CPU_TYPE_ENTRY(T1020, T1020, 0), 76 CPU_TYPE_ENTRY(T1021, T1021, 0), 77 CPU_TYPE_ENTRY(T1022, T1022, 0), 78 CPU_TYPE_ENTRY(BSC9130, 9130, 1), 79 CPU_TYPE_ENTRY(BSC9131, 9131, 1), 80 CPU_TYPE_ENTRY(BSC9132, 9132, 2), 81 CPU_TYPE_ENTRY(BSC9232, 9232, 2), 82 CPU_TYPE_ENTRY(C291, C291, 1), 83 CPU_TYPE_ENTRY(C292, C292, 1), 84 CPU_TYPE_ENTRY(C293, C293, 1), 85 #elif defined(CONFIG_MPC86xx) 86 CPU_TYPE_ENTRY(8610, 8610, 1), 87 CPU_TYPE_ENTRY(8641, 8641, 2), 88 CPU_TYPE_ENTRY(8641D, 8641D, 2), 89 #endif 90 }; 91 92 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 93 static inline u32 init_type(u32 cluster, int init_id) 94 { 95 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 96 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; 97 u32 type = in_be32(&gur->tp_ityp[idx]); 98 99 if (type & TP_ITYP_AV) 100 return type; 101 102 return 0; 103 } 104 105 u32 compute_ppc_cpumask(void) 106 { 107 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 108 int i = 0, count = 0; 109 u32 cluster, type, mask = 0; 110 111 do { 112 int j; 113 cluster = in_be32(&gur->tp_cluster[i].lower); 114 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 115 type = init_type(cluster, j); 116 if (type) { 117 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 118 mask |= 1 << count; 119 count++; 120 } 121 } 122 i++; 123 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 124 125 return mask; 126 } 127 128 int fsl_qoriq_core_to_cluster(unsigned int core) 129 { 130 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 131 int i = 0, count = 0; 132 u32 cluster; 133 134 do { 135 int j; 136 cluster = in_be32(&gur->tp_cluster[i].lower); 137 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { 138 if (init_type(cluster, j)) { 139 if (count == core) 140 return i; 141 count++; 142 } 143 } 144 i++; 145 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); 146 147 return -1; /* cannot identify the cluster */ 148 } 149 150 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 151 /* 152 * Before chassis genenration 2, the cpumask should be hard-coded. 153 * In case of cpu type unknown or cpumask unset, use 1 as fail save. 154 */ 155 #define compute_ppc_cpumask() 1 156 #define fsl_qoriq_core_to_cluster(x) x 157 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 158 159 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); 160 161 struct cpu_type *identify_cpu(u32 ver) 162 { 163 int i; 164 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { 165 if (cpu_type_list[i].soc_ver == ver) 166 return &cpu_type_list[i]; 167 } 168 return &cpu_type_unknown; 169 } 170 171 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 172 #define MPC8xxx_PICFRR_NCPU_SHIFT 8 173 174 /* 175 * Return a 32-bit mask indicating which cores are present on this SOC. 176 */ 177 u32 cpu_mask(void) 178 { 179 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; 180 struct cpu_type *cpu = gd->arch.cpu; 181 182 /* better to query feature reporting register than just assume 1 */ 183 if (cpu == &cpu_type_unknown) 184 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> 185 MPC8xxx_PICFRR_NCPU_SHIFT) + 1; 186 187 if (cpu->num_cores == 0) 188 return compute_ppc_cpumask(); 189 190 return cpu->mask; 191 } 192 193 /* 194 * Return the number of cores on this SOC. 195 */ 196 int cpu_numcores(void) 197 { 198 struct cpu_type *cpu = gd->arch.cpu; 199 200 /* 201 * Report # of cores in terms of the cpu_mask if we haven't 202 * figured out how many there are yet 203 */ 204 if (cpu->num_cores == 0) 205 return hweight32(cpu_mask()); 206 207 return cpu->num_cores; 208 } 209 210 /* 211 * Check if the given core ID is valid 212 * 213 * Returns zero if it isn't, 1 if it is. 214 */ 215 int is_core_valid(unsigned int core) 216 { 217 return !!((1 << core) & cpu_mask()); 218 } 219 220 int probecpu (void) 221 { 222 uint svr; 223 uint ver; 224 225 svr = get_svr(); 226 ver = SVR_SOC_VER(svr); 227 228 gd->arch.cpu = identify_cpu(ver); 229 230 return 0; 231 } 232 233 /* Once in memory, compute mask & # cores once and save them off */ 234 int fixup_cpu(void) 235 { 236 struct cpu_type *cpu = gd->arch.cpu; 237 238 if (cpu->num_cores == 0) { 239 cpu->mask = cpu_mask(); 240 cpu->num_cores = cpu_numcores(); 241 } 242 243 return 0; 244 } 245 246 /* 247 * Initializes on-chip ethernet controllers. 248 * to override, implement board_eth_init() 249 */ 250 int cpu_eth_init(bd_t *bis) 251 { 252 #if defined(CONFIG_ETHER_ON_FCC) 253 fec_initialize(bis); 254 #endif 255 256 #if defined(CONFIG_UEC_ETH) 257 uec_standard_init(bis); 258 #endif 259 260 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) 261 tsec_standard_init(bis); 262 #endif 263 264 #ifdef CONFIG_FMAN_ENET 265 fm_standard_init(bis); 266 #endif 267 return 0; 268 } 269