xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision fabbeb33) 
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
4 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 */
7
8/*  U-Boot - Startup Code for PowerPC based Embedded Boards
9 *
10 *
11 *  The processor starts at 0x00000100 and the code is executed
12 *  from flash. The code is organized to be at an other address
13 *  in memory, but as long we don't jump around before relocating,
14 *  board_init lies at a quite high address and when the cpu has
15 *  jumped there, everything is ok.
16 *  This works because the cpu gives the FLASH (CS0) the whole
17 *  address space at startup, and board_init lies as a echo of
18 *  the flash somewhere up there in the memory map.
19 *
20 *  board_init will change CS0 to be positioned at the correct
21 *  address and (s)dram will be positioned at address 0
22 */
23#include <asm-offsets.h>
24#include <config.h>
25#include <mpc8xx.h>
26#include <version.h>
27
28#include <ppc_asm.tmpl>
29#include <ppc_defs.h>
30
31#include <asm/cache.h>
32#include <asm/mmu.h>
33#include <asm/u-boot.h>
34
35/* We don't want the  MMU yet.
36*/
37#undef	MSR_KERNEL
38#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
39
40/*
41 * Set up GOT: Global Offset Table
42 *
43 * Use r12 to access the GOT
44 */
45	START_GOT
46	GOT_ENTRY(_GOT2_TABLE_)
47	GOT_ENTRY(_FIXUP_TABLE_)
48
49	GOT_ENTRY(_start)
50	GOT_ENTRY(_start_of_vectors)
51	GOT_ENTRY(_end_of_vectors)
52	GOT_ENTRY(transfer_to_handler)
53
54	GOT_ENTRY(__init_end)
55	GOT_ENTRY(__bss_end)
56	GOT_ENTRY(__bss_start)
57	END_GOT
58
59/*
60 * r3 - 1st arg to board_init(): IMMP pointer
61 * r4 - 2nd arg to board_init(): boot flag
62 */
63	.text
64	.long	0x27051956		/* U-Boot Magic Number			*/
65	.globl	version_string
66version_string:
67	.ascii U_BOOT_VERSION_STRING, "\0"
68
69	. = EXC_OFF_SYS_RESET
70	.globl	_start
71_start:
72	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
73	mtspr	638, r3
74
75	/* Initialize machine status; enable machine check interrupt		*/
76	/*----------------------------------------------------------------------*/
77	li	r3, MSR_KERNEL		/* Set ME, RI flags */
78	mtmsr	r3
79	mtspr	SRR1, r3		/* Make SRR1 match MSR */
80
81	mfspr	r3, ICR			/* clear Interrupt Cause Register */
82
83	/* Initialize debug port registers					*/
84	/*----------------------------------------------------------------------*/
85	xor	r0, r0, r0		/* Clear R0 */
86	mtspr	LCTRL1, r0		/* Initialize debug port regs */
87	mtspr	LCTRL2, r0
88	mtspr	COUNTA, r0
89	mtspr	COUNTB, r0
90
91	/* Reset the caches							*/
92	/*----------------------------------------------------------------------*/
93
94	mfspr	r3, IC_CST		/* Clear error bits */
95	mfspr	r3, DC_CST
96
97	lis	r3, IDC_UNALL@h		/* Unlock all */
98	mtspr	IC_CST, r3
99	mtspr	DC_CST, r3
100
101	lis	r3, IDC_INVALL@h	/* Invalidate all */
102	mtspr	IC_CST, r3
103	mtspr	DC_CST, r3
104
105	lis	r3, IDC_DISABLE@h	/* Disable data cache */
106	mtspr	DC_CST, r3
107
108	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
109	mtspr	IC_CST, r3
110
111	/* invalidate all tlb's							*/
112	/*----------------------------------------------------------------------*/
113
114	tlbia
115	isync
116
117	/*
118	 * Calculate absolute address in FLASH and jump there
119	 *----------------------------------------------------------------------*/
120
121	lis	r3, CONFIG_SYS_MONITOR_BASE@h
122	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
123	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
124	mtlr	r3
125	blr
126
127in_flash:
128
129	/* initialize some SPRs that are hard to access from C			*/
130	/*----------------------------------------------------------------------*/
131
132	/*
133	 * Disable serialized ifetch and show cycles
134	 * (i.e. set processor to normal mode).
135	 * This is also a silicon bug workaround, see errata
136	 */
137
138	li	r2, 0x0007
139	mtspr	ICTRL, r2
140
141	/* Set up debug mode entry */
142
143	lis	r2, CONFIG_SYS_DER@h
144	ori	r2, r2, CONFIG_SYS_DER@l
145	mtspr	DER, r2
146
147	/* set up the stack on top of internal DPRAM */
148	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
149	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
150	stw	r0, -4(r3)
151	stw	r0, -8(r3)
152	addi	r1, r3, -8
153
154	bl	board_init_f_alloc_reserve
155	addi	r1, r3, -8
156
157	/* Zeroise the CPM dpram */
158	lis	r4, CONFIG_SYS_IMMR@h
159	ori	r4, r4, (0x2000 - 4)
160	li	r0, (0x2000 / 4)
161	mtctr	r0
162	li	r0, 0
1631:	stwu	r0, 4(r4)
164	bdnz	1b
165
166	bl	board_init_f_init_reserve
167
168	/* let the C-code set up the rest					*/
169	/*									*/
170	/* Be careful to keep code relocatable !				*/
171	/*----------------------------------------------------------------------*/
172
173	GET_GOT			/* initialize GOT access			*/
174
175	lis	r3, CONFIG_SYS_IMMR@h
176	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
177
178	bl	board_init_f	/* run 1st part of board init code (from Flash) */
179
180	/* NOTREACHED - board_init_f() does not return */
181
182
183	.globl	_start_of_vectors
184_start_of_vectors:
185
186/* Machine check */
187	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
188
189/* Data Storage exception.  "Never" generated on the 860. */
190	STD_EXCEPTION(0x300, DataStorage, UnknownException)
191
192/* Instruction Storage exception.  "Never" generated on the 860. */
193	STD_EXCEPTION(0x400, InstStorage, UnknownException)
194
195/* External Interrupt exception. */
196	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
197
198/* Alignment exception. */
199	. = 0x600
200Alignment:
201	EXCEPTION_PROLOG(SRR0, SRR1)
202	mfspr	r4,DAR
203	stw	r4,_DAR(r21)
204	mfspr	r5,DSISR
205	stw	r5,_DSISR(r21)
206	addi	r3,r1,STACK_FRAME_OVERHEAD
207	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
208
209/* Program check exception */
210	. = 0x700
211ProgramCheck:
212	EXCEPTION_PROLOG(SRR0, SRR1)
213	addi	r3,r1,STACK_FRAME_OVERHEAD
214	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
215		MSR_KERNEL, COPY_EE)
216
217	/* No FPU on MPC8xx.  This exception is not supposed to happen.
218	*/
219	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
220
221	/* I guess we could implement decrementer, and may have
222	 * to someday for timekeeping.
223	 */
224	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
225	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
226	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
227	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
228	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
229
230	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
231	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
232
233	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
234	 * for all unimplemented and illegal instructions.
235	 */
236	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
237
238	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
239	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
240	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
241	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
242
243	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
244	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
245	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
246	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
247	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
248	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
249	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
250
251	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
252	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
253	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
254	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
255
256
257	.globl	_end_of_vectors
258_end_of_vectors:
259
260
261	. = 0x2000
262
263/*
264 * This code finishes saving the registers to the exception frame
265 * and jumps to the appropriate handler for the exception.
266 * Register r21 is pointer into trap frame, r1 has new stack pointer.
267 */
268	.globl	transfer_to_handler
269transfer_to_handler:
270	stw	r22,_NIP(r21)
271	lis	r22,MSR_POW@h
272	andc	r23,r23,r22
273	stw	r23,_MSR(r21)
274	SAVE_GPR(7, r21)
275	SAVE_4GPRS(8, r21)
276	SAVE_8GPRS(12, r21)
277	SAVE_8GPRS(24, r21)
278	mflr	r23
279	andi.	r24,r23,0x3f00		/* get vector offset */
280	stw	r24,TRAP(r21)
281	li	r22,0
282	stw	r22,RESULT(r21)
283	mtspr	SPRG2,r22		/* r1 is now kernel sp */
284	lwz	r24,0(r23)		/* virtual address of handler */
285	lwz	r23,4(r23)		/* where to go when done */
286	mtspr	SRR0,r24
287	mtspr	SRR1,r20
288	mtlr	r23
289	SYNC
290	rfi				/* jump to handler, enable MMU */
291
292int_return:
293	mfmsr	r28			/* Disable interrupts */
294	li	r4,0
295	ori	r4,r4,MSR_EE
296	andc	r28,r28,r4
297	SYNC				/* Some chip revs need this... */
298	mtmsr	r28
299	SYNC
300	lwz	r2,_CTR(r1)
301	lwz	r0,_LINK(r1)
302	mtctr	r2
303	mtlr	r0
304	lwz	r2,_XER(r1)
305	lwz	r0,_CCR(r1)
306	mtspr	XER,r2
307	mtcrf	0xFF,r0
308	REST_10GPRS(3, r1)
309	REST_10GPRS(13, r1)
310	REST_8GPRS(23, r1)
311	REST_GPR(31, r1)
312	lwz	r2,_NIP(r1)		/* Restore environment */
313	lwz	r0,_MSR(r1)
314	mtspr	SRR0,r2
315	mtspr	SRR1,r0
316	lwz	r0,GPR0(r1)
317	lwz	r2,GPR2(r1)
318	lwz	r1,GPR1(r1)
319	SYNC
320	rfi
321
322/*------------------------------------------------------------------------------*/
323
324/*
325 * void relocate_code (addr_sp, gd, addr_moni)
326 *
327 * This "function" does not return, instead it continues in RAM
328 * after relocating the monitor code.
329 *
330 * r3 = dest
331 * r4 = src
332 * r5 = length in bytes
333 * r6 = cachelinesize
334 */
335	.globl	relocate_code
336relocate_code:
337	mr	r1,  r3		/* Set new stack pointer		*/
338	mr	r9,  r4		/* Save copy of Global Data pointer	*/
339	mr	r10, r5		/* Save copy of Destination Address	*/
340
341	GET_GOT
342	mr	r3,  r5				/* Destination Address	*/
343	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
344	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
345	lwz	r5, GOT(__init_end)
346	sub	r5, r5, r4
347	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
348
349	/*
350	 * Fix GOT pointer:
351	 *
352	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
353	 *
354	 * Offset:
355	 */
356	sub	r15, r10, r4
357
358	/* First our own GOT */
359	add	r12, r12, r15
360	/* then the one used by the C code */
361	add	r30, r30, r15
362
363	/*
364	 * Now relocate code
365	 */
366
367	cmplw	cr1,r3,r4
368	addi	r0,r5,3
369	srwi.	r0,r0,2
370	beq	cr1,4f		/* In place copy is not necessary	*/
371	beq	7f		/* Protect against 0 count		*/
372	mtctr	r0
373	bge	cr1,2f
374
375	la	r8,-4(r4)
376	la	r7,-4(r3)
3771:	lwzu	r0,4(r8)
378	stwu	r0,4(r7)
379	bdnz	1b
380	b	4f
381
3822:	slwi	r0,r0,2
383	add	r8,r4,r0
384	add	r7,r3,r0
3853:	lwzu	r0,-4(r8)
386	stwu	r0,-4(r7)
387	bdnz	3b
388
389/*
390 * Now flush the cache: note that we must start from a cache aligned
391 * address. Otherwise we might miss one cache line.
392 */
3934:	cmpwi	r6,0
394	add	r5,r3,r5
395	beq	7f		/* Always flush prefetch queue in any case */
396	subi	r0,r6,1
397	andc	r3,r3,r0
398	mr	r4,r3
3995:	dcbst	0,r4
400	add	r4,r4,r6
401	cmplw	r4,r5
402	blt	5b
403	sync			/* Wait for all dcbst to complete on bus */
404	mr	r4,r3
4056:	icbi	0,r4
406	add	r4,r4,r6
407	cmplw	r4,r5
408	blt	6b
4097:	sync			/* Wait for all icbi to complete on bus	*/
410	isync
411
412/*
413 * We are done. Do not return, instead branch to second part of board
414 * initialization, now running from RAM.
415 */
416
417	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
418	mtlr	r0
419	blr
420
421in_ram:
422
423	/*
424	 * Relocation Function, r12 point to got2+0x8000
425	 *
426	 * Adjust got2 pointers, no need to check for 0, this code
427	 * already puts a few entries in the table.
428	 */
429	li	r0,__got2_entries@sectoff@l
430	la	r3,GOT(_GOT2_TABLE_)
431	lwz	r11,GOT(_GOT2_TABLE_)
432	mtctr	r0
433	sub	r11,r3,r11
434	addi	r3,r3,-4
4351:	lwzu	r0,4(r3)
436	cmpwi	r0,0
437	beq-	2f
438	add	r0,r0,r11
439	stw	r0,0(r3)
4402:	bdnz	1b
441
442	/*
443	 * Now adjust the fixups and the pointers to the fixups
444	 * in case we need to move ourselves again.
445	 */
446	li	r0,__fixup_entries@sectoff@l
447	lwz	r3,GOT(_FIXUP_TABLE_)
448	cmpwi	r0,0
449	mtctr	r0
450	addi	r3,r3,-4
451	beq	4f
4523:	lwzu	r4,4(r3)
453	lwzux	r0,r4,r11
454	cmpwi	r0,0
455	add	r0,r0,r11
456	stw	r4,0(r3)
457	beq-	5f
458	stw	r0,0(r4)
4595:	bdnz	3b
4604:
461clear_bss:
462	/*
463	 * Now clear BSS segment
464	 */
465	lwz	r3,GOT(__bss_start)
466	lwz	r4,GOT(__bss_end)
467
468	cmplw	0, r3, r4
469	beq	6f
470
471	li	r0, 0
4725:
473	stw	r0, 0(r3)
474	addi	r3, r3, 4
475	cmplw	0, r3, r4
476	bne	5b
4776:
478
479	mr	r3, r9		/* Global Data pointer		*/
480	mr	r4, r10		/* Destination Address		*/
481	bl	board_init_r
482
483	/*
484	 * Copy exception vector code to low memory
485	 *
486	 * r3: dest_addr
487	 * r7: source address, r8: end address, r9: target address
488	 */
489	.globl	trap_init
490trap_init:
491	mflr	r4			/* save link register		*/
492	GET_GOT
493	lwz	r7, GOT(_start)
494	lwz	r8, GOT(_end_of_vectors)
495
496	li	r9, 0x100		/* reset vector always at 0x100 */
497
498	cmplw	0, r7, r8
499	bgelr				/* return if r7>=r8 - just in case */
5001:
501	lwz	r0, 0(r7)
502	stw	r0, 0(r9)
503	addi	r7, r7, 4
504	addi	r9, r9, 4
505	cmplw	0, r7, r8
506	bne	1b
507
508	/*
509	 * relocate `hdlr' and `int_return' entries
510	 */
511	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
512	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
5132:
514	bl	trap_reloc
515	addi	r7, r7, 0x100		/* next exception vector	*/
516	cmplw	0, r7, r8
517	blt	2b
518
519	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
520	bl	trap_reloc
521
522	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
523	bl	trap_reloc
524
525	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
526	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
5273:
528	bl	trap_reloc
529	addi	r7, r7, 0x100		/* next exception vector	*/
530	cmplw	0, r7, r8
531	blt	3b
532
533	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
534	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5354:
536	bl	trap_reloc
537	addi	r7, r7, 0x100		/* next exception vector	*/
538	cmplw	0, r7, r8
539	blt	4b
540
541	mtlr	r4			/* restore link register	*/
542	blr
543