xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision f9727161) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#define CONFIG_8xx 1		/* needed for Linux kernel header files */
30#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
31
32#include <ppc_asm.tmpl>
33#include <ppc_defs.h>
34
35#include <asm/cache.h>
36#include <asm/mmu.h>
37#include <asm/u-boot.h>
38
39/* We don't want the  MMU yet.
40*/
41#undef	MSR_KERNEL
42#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
43
44/*
45 * Set up GOT: Global Offset Table
46 *
47 * Use r12 to access the GOT
48 */
49	START_GOT
50	GOT_ENTRY(_GOT2_TABLE_)
51	GOT_ENTRY(_FIXUP_TABLE_)
52
53	GOT_ENTRY(_start)
54	GOT_ENTRY(_start_of_vectors)
55	GOT_ENTRY(_end_of_vectors)
56	GOT_ENTRY(transfer_to_handler)
57
58	GOT_ENTRY(__init_end)
59	GOT_ENTRY(__bss_end)
60	GOT_ENTRY(__bss_start)
61	END_GOT
62
63/*
64 * r3 - 1st arg to board_init(): IMMP pointer
65 * r4 - 2nd arg to board_init(): boot flag
66 */
67	.text
68	.long	0x27051956		/* U-Boot Magic Number			*/
69	.globl	version_string
70version_string:
71	.ascii U_BOOT_VERSION_STRING, "\0"
72
73	. = EXC_OFF_SYS_RESET
74	.globl	_start
75_start:
76	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
77	mtspr	638, r3
78
79	/* Initialize machine status; enable machine check interrupt		*/
80	/*----------------------------------------------------------------------*/
81	li	r3, MSR_KERNEL		/* Set ME, RI flags */
82	mtmsr	r3
83	mtspr	SRR1, r3		/* Make SRR1 match MSR */
84
85	mfspr	r3, ICR			/* clear Interrupt Cause Register */
86
87	/* Initialize debug port registers					*/
88	/*----------------------------------------------------------------------*/
89	xor	r0, r0, r0		/* Clear R0 */
90	mtspr	LCTRL1, r0		/* Initialize debug port regs */
91	mtspr	LCTRL2, r0
92	mtspr	COUNTA, r0
93	mtspr	COUNTB, r0
94
95	/* Reset the caches							*/
96	/*----------------------------------------------------------------------*/
97
98	mfspr	r3, IC_CST		/* Clear error bits */
99	mfspr	r3, DC_CST
100
101	lis	r3, IDC_UNALL@h		/* Unlock all */
102	mtspr	IC_CST, r3
103	mtspr	DC_CST, r3
104
105	lis	r3, IDC_INVALL@h	/* Invalidate all */
106	mtspr	IC_CST, r3
107	mtspr	DC_CST, r3
108
109	lis	r3, IDC_DISABLE@h	/* Disable data cache */
110	mtspr	DC_CST, r3
111
112#if !defined(CONFIG_SYS_DELAYED_ICACHE)
113					/* On IP860 and PCU E,
114					 * we cannot enable IC yet
115					 */
116	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
117#endif
118	mtspr	IC_CST, r3
119
120	/* invalidate all tlb's							*/
121	/*----------------------------------------------------------------------*/
122
123	tlbia
124	isync
125
126	/*
127	 * Calculate absolute address in FLASH and jump there
128	 *----------------------------------------------------------------------*/
129
130	lis	r3, CONFIG_SYS_MONITOR_BASE@h
131	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
132	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
133	mtlr	r3
134	blr
135
136in_flash:
137
138	/* initialize some SPRs that are hard to access from C			*/
139	/*----------------------------------------------------------------------*/
140
141	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
142	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
143	/* Note: R0 is still 0 here */
144	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
145	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
146
147	/*
148	 * Disable serialized ifetch and show cycles
149	 * (i.e. set processor to normal mode).
150	 * This is also a silicon bug workaround, see errata
151	 */
152
153	li	r2, 0x0007
154	mtspr	ICTRL, r2
155
156	/* Set up debug mode entry */
157
158	lis	r2, CONFIG_SYS_DER@h
159	ori	r2, r2, CONFIG_SYS_DER@l
160	mtspr	DER, r2
161
162	/* let the C-code set up the rest					*/
163	/*									*/
164	/* Be careful to keep code relocatable !				*/
165	/*----------------------------------------------------------------------*/
166
167	GET_GOT			/* initialize GOT access			*/
168
169	/* r3: IMMR */
170	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
171
172	bl	board_init_f	/* run 1st part of board init code (from Flash) */
173
174	/* NOTREACHED - board_init_f() does not return */
175
176
177	.globl	_start_of_vectors
178_start_of_vectors:
179
180/* Machine check */
181	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
182
183/* Data Storage exception.  "Never" generated on the 860. */
184	STD_EXCEPTION(0x300, DataStorage, UnknownException)
185
186/* Instruction Storage exception.  "Never" generated on the 860. */
187	STD_EXCEPTION(0x400, InstStorage, UnknownException)
188
189/* External Interrupt exception. */
190	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
191
192/* Alignment exception. */
193	. = 0x600
194Alignment:
195	EXCEPTION_PROLOG(SRR0, SRR1)
196	mfspr	r4,DAR
197	stw	r4,_DAR(r21)
198	mfspr	r5,DSISR
199	stw	r5,_DSISR(r21)
200	addi	r3,r1,STACK_FRAME_OVERHEAD
201	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
202
203/* Program check exception */
204	. = 0x700
205ProgramCheck:
206	EXCEPTION_PROLOG(SRR0, SRR1)
207	addi	r3,r1,STACK_FRAME_OVERHEAD
208	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
209		MSR_KERNEL, COPY_EE)
210
211	/* No FPU on MPC8xx.  This exception is not supposed to happen.
212	*/
213	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
214
215	/* I guess we could implement decrementer, and may have
216	 * to someday for timekeeping.
217	 */
218	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
219	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
220	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
221	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
222	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
223
224	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
225	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
226
227	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
228	 * for all unimplemented and illegal instructions.
229	 */
230	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
231
232	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
233	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
234	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
235	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
236
237	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
238	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
239	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
240	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
241	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
242	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
243	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
244
245	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
246	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
247	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
248	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
249
250
251	.globl	_end_of_vectors
252_end_of_vectors:
253
254
255	. = 0x2000
256
257/*
258 * This code finishes saving the registers to the exception frame
259 * and jumps to the appropriate handler for the exception.
260 * Register r21 is pointer into trap frame, r1 has new stack pointer.
261 */
262	.globl	transfer_to_handler
263transfer_to_handler:
264	stw	r22,_NIP(r21)
265	lis	r22,MSR_POW@h
266	andc	r23,r23,r22
267	stw	r23,_MSR(r21)
268	SAVE_GPR(7, r21)
269	SAVE_4GPRS(8, r21)
270	SAVE_8GPRS(12, r21)
271	SAVE_8GPRS(24, r21)
272	mflr	r23
273	andi.	r24,r23,0x3f00		/* get vector offset */
274	stw	r24,TRAP(r21)
275	li	r22,0
276	stw	r22,RESULT(r21)
277	mtspr	SPRG2,r22		/* r1 is now kernel sp */
278	lwz	r24,0(r23)		/* virtual address of handler */
279	lwz	r23,4(r23)		/* where to go when done */
280	mtspr	SRR0,r24
281	mtspr	SRR1,r20
282	mtlr	r23
283	SYNC
284	rfi				/* jump to handler, enable MMU */
285
286int_return:
287	mfmsr	r28			/* Disable interrupts */
288	li	r4,0
289	ori	r4,r4,MSR_EE
290	andc	r28,r28,r4
291	SYNC				/* Some chip revs need this... */
292	mtmsr	r28
293	SYNC
294	lwz	r2,_CTR(r1)
295	lwz	r0,_LINK(r1)
296	mtctr	r2
297	mtlr	r0
298	lwz	r2,_XER(r1)
299	lwz	r0,_CCR(r1)
300	mtspr	XER,r2
301	mtcrf	0xFF,r0
302	REST_10GPRS(3, r1)
303	REST_10GPRS(13, r1)
304	REST_8GPRS(23, r1)
305	REST_GPR(31, r1)
306	lwz	r2,_NIP(r1)		/* Restore environment */
307	lwz	r0,_MSR(r1)
308	mtspr	SRR0,r2
309	mtspr	SRR1,r0
310	lwz	r0,GPR0(r1)
311	lwz	r2,GPR2(r1)
312	lwz	r1,GPR1(r1)
313	SYNC
314	rfi
315
316/* Cache functions.
317*/
318	.globl	icache_enable
319icache_enable:
320	SYNC
321	lis	r3, IDC_INVALL@h
322	mtspr	IC_CST, r3
323	lis	r3, IDC_ENABLE@h
324	mtspr	IC_CST, r3
325	blr
326
327	.globl	icache_disable
328icache_disable:
329	SYNC
330	lis	r3, IDC_DISABLE@h
331	mtspr	IC_CST, r3
332	blr
333
334	.globl	icache_status
335icache_status:
336	mfspr	r3, IC_CST
337	srwi	r3, r3, 31	/* >>31 => select bit 0 */
338	blr
339
340	.globl	dcache_enable
341dcache_enable:
342#if 0
343	SYNC
344#endif
345#if 1
346	lis	r3, 0x0400		/* Set cache mode with MMU off */
347	mtspr	MD_CTR, r3
348#endif
349
350	lis	r3, IDC_INVALL@h
351	mtspr	DC_CST, r3
352#if 0
353	lis	r3, DC_SFWT@h
354	mtspr	DC_CST, r3
355#endif
356	lis	r3, IDC_ENABLE@h
357	mtspr	DC_CST, r3
358	blr
359
360	.globl	dcache_disable
361dcache_disable:
362	SYNC
363	lis	r3, IDC_DISABLE@h
364	mtspr	DC_CST, r3
365	lis	r3, IDC_INVALL@h
366	mtspr	DC_CST, r3
367	blr
368
369	.globl	dcache_status
370dcache_status:
371	mfspr	r3, DC_CST
372	srwi	r3, r3, 31	/* >>31 => select bit 0 */
373	blr
374
375	.globl	dc_read
376dc_read:
377	mtspr	DC_ADR, r3
378	mfspr	r3, DC_DAT
379	blr
380
381/*
382 * unsigned int get_immr (unsigned int mask)
383 *
384 * return (mask ? (IMMR & mask) : IMMR);
385 */
386	.globl	get_immr
387get_immr:
388	mr	r4,r3		/* save mask */
389	mfspr	r3, IMMR	/* IMMR */
390	cmpwi	0,r4,0		/* mask != 0 ? */
391	beq	4f
392	and	r3,r3,r4	/* IMMR & mask */
3934:
394	blr
395
396	.globl get_pvr
397get_pvr:
398	mfspr	r3, PVR
399	blr
400
401
402	.globl wr_ic_cst
403wr_ic_cst:
404	mtspr	IC_CST, r3
405	blr
406
407	.globl rd_ic_cst
408rd_ic_cst:
409	mfspr	r3, IC_CST
410	blr
411
412	.globl wr_ic_adr
413wr_ic_adr:
414	mtspr	IC_ADR, r3
415	blr
416
417
418	.globl wr_dc_cst
419wr_dc_cst:
420	mtspr	DC_CST, r3
421	blr
422
423	.globl rd_dc_cst
424rd_dc_cst:
425	mfspr	r3, DC_CST
426	blr
427
428	.globl wr_dc_adr
429wr_dc_adr:
430	mtspr	DC_ADR, r3
431	blr
432
433/*------------------------------------------------------------------------------*/
434
435/*
436 * void relocate_code (addr_sp, gd, addr_moni)
437 *
438 * This "function" does not return, instead it continues in RAM
439 * after relocating the monitor code.
440 *
441 * r3 = dest
442 * r4 = src
443 * r5 = length in bytes
444 * r6 = cachelinesize
445 */
446	.globl	relocate_code
447relocate_code:
448	mr	r1,  r3		/* Set new stack pointer		*/
449	mr	r9,  r4		/* Save copy of Global Data pointer	*/
450	mr	r10, r5		/* Save copy of Destination Address	*/
451
452	GET_GOT
453	mr	r3,  r5				/* Destination Address	*/
454	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
455	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
456	lwz	r5, GOT(__init_end)
457	sub	r5, r5, r4
458	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
459
460	/*
461	 * Fix GOT pointer:
462	 *
463	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
464	 *
465	 * Offset:
466	 */
467	sub	r15, r10, r4
468
469	/* First our own GOT */
470	add	r12, r12, r15
471	/* then the one used by the C code */
472	add	r30, r30, r15
473
474	/*
475	 * Now relocate code
476	 */
477
478	cmplw	cr1,r3,r4
479	addi	r0,r5,3
480	srwi.	r0,r0,2
481	beq	cr1,4f		/* In place copy is not necessary	*/
482	beq	7f		/* Protect against 0 count		*/
483	mtctr	r0
484	bge	cr1,2f
485
486	la	r8,-4(r4)
487	la	r7,-4(r3)
4881:	lwzu	r0,4(r8)
489	stwu	r0,4(r7)
490	bdnz	1b
491	b	4f
492
4932:	slwi	r0,r0,2
494	add	r8,r4,r0
495	add	r7,r3,r0
4963:	lwzu	r0,-4(r8)
497	stwu	r0,-4(r7)
498	bdnz	3b
499
500/*
501 * Now flush the cache: note that we must start from a cache aligned
502 * address. Otherwise we might miss one cache line.
503 */
5044:	cmpwi	r6,0
505	add	r5,r3,r5
506	beq	7f		/* Always flush prefetch queue in any case */
507	subi	r0,r6,1
508	andc	r3,r3,r0
509	mr	r4,r3
5105:	dcbst	0,r4
511	add	r4,r4,r6
512	cmplw	r4,r5
513	blt	5b
514	sync			/* Wait for all dcbst to complete on bus */
515	mr	r4,r3
5166:	icbi	0,r4
517	add	r4,r4,r6
518	cmplw	r4,r5
519	blt	6b
5207:	sync			/* Wait for all icbi to complete on bus	*/
521	isync
522
523/*
524 * We are done. Do not return, instead branch to second part of board
525 * initialization, now running from RAM.
526 */
527
528	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
529	mtlr	r0
530	blr
531
532in_ram:
533
534	/*
535	 * Relocation Function, r12 point to got2+0x8000
536	 *
537	 * Adjust got2 pointers, no need to check for 0, this code
538	 * already puts a few entries in the table.
539	 */
540	li	r0,__got2_entries@sectoff@l
541	la	r3,GOT(_GOT2_TABLE_)
542	lwz	r11,GOT(_GOT2_TABLE_)
543	mtctr	r0
544	sub	r11,r3,r11
545	addi	r3,r3,-4
5461:	lwzu	r0,4(r3)
547	cmpwi	r0,0
548	beq-	2f
549	add	r0,r0,r11
550	stw	r0,0(r3)
5512:	bdnz	1b
552
553	/*
554	 * Now adjust the fixups and the pointers to the fixups
555	 * in case we need to move ourselves again.
556	 */
557	li	r0,__fixup_entries@sectoff@l
558	lwz	r3,GOT(_FIXUP_TABLE_)
559	cmpwi	r0,0
560	mtctr	r0
561	addi	r3,r3,-4
562	beq	4f
5633:	lwzu	r4,4(r3)
564	lwzux	r0,r4,r11
565	cmpwi	r0,0
566	add	r0,r0,r11
567	stw	r4,0(r3)
568	beq-	5f
569	stw	r0,0(r4)
5705:	bdnz	3b
5714:
572clear_bss:
573	/*
574	 * Now clear BSS segment
575	 */
576	lwz	r3,GOT(__bss_start)
577	lwz	r4,GOT(__bss_end)
578
579	cmplw	0, r3, r4
580	beq	6f
581
582	li	r0, 0
5835:
584	stw	r0, 0(r3)
585	addi	r3, r3, 4
586	cmplw	0, r3, r4
587	bne	5b
5886:
589
590	mr	r3, r9		/* Global Data pointer		*/
591	mr	r4, r10		/* Destination Address		*/
592	bl	board_init_r
593
594	/*
595	 * Copy exception vector code to low memory
596	 *
597	 * r3: dest_addr
598	 * r7: source address, r8: end address, r9: target address
599	 */
600	.globl	trap_init
601trap_init:
602	mflr	r4			/* save link register		*/
603	GET_GOT
604	lwz	r7, GOT(_start)
605	lwz	r8, GOT(_end_of_vectors)
606
607	li	r9, 0x100		/* reset vector always at 0x100 */
608
609	cmplw	0, r7, r8
610	bgelr				/* return if r7>=r8 - just in case */
6111:
612	lwz	r0, 0(r7)
613	stw	r0, 0(r9)
614	addi	r7, r7, 4
615	addi	r9, r9, 4
616	cmplw	0, r7, r8
617	bne	1b
618
619	/*
620	 * relocate `hdlr' and `int_return' entries
621	 */
622	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
623	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6242:
625	bl	trap_reloc
626	addi	r7, r7, 0x100		/* next exception vector	*/
627	cmplw	0, r7, r8
628	blt	2b
629
630	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
631	bl	trap_reloc
632
633	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
634	bl	trap_reloc
635
636	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
637	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6383:
639	bl	trap_reloc
640	addi	r7, r7, 0x100		/* next exception vector	*/
641	cmplw	0, r7, r8
642	blt	3b
643
644	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
645	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6464:
647	bl	trap_reloc
648	addi	r7, r7, 0x100		/* next exception vector	*/
649	cmplw	0, r7, r8
650	blt	4b
651
652	mtlr	r4			/* restore link register	*/
653	blr
654