xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision ee943655) 
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
4 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 */
7
8/*  U-Boot - Startup Code for PowerPC based Embedded Boards
9 *
10 *
11 *  The processor starts at 0x00000100 and the code is executed
12 *  from flash. The code is organized to be at an other address
13 *  in memory, but as long we don't jump around before relocating,
14 *  board_init lies at a quite high address and when the cpu has
15 *  jumped there, everything is ok.
16 *  This works because the cpu gives the FLASH (CS0) the whole
17 *  address space at startup, and board_init lies as a echo of
18 *  the flash somewhere up there in the memory map.
19 *
20 *  board_init will change CS0 to be positioned at the correct
21 *  address and (s)dram will be positioned at address 0
22 */
23#include <asm-offsets.h>
24#include <config.h>
25#include <mpc8xx.h>
26#include <version.h>
27
28#include <ppc_asm.tmpl>
29#include <ppc_defs.h>
30
31#include <asm/cache.h>
32#include <asm/mmu.h>
33#include <asm/u-boot.h>
34
35/* We don't want the  MMU yet.
36*/
37#undef	MSR_KERNEL
38#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
39
40/*
41 * Set up GOT: Global Offset Table
42 *
43 * Use r12 to access the GOT
44 */
45	START_GOT
46	GOT_ENTRY(_GOT2_TABLE_)
47	GOT_ENTRY(_FIXUP_TABLE_)
48
49	GOT_ENTRY(_start)
50	GOT_ENTRY(_start_of_vectors)
51	GOT_ENTRY(_end_of_vectors)
52	GOT_ENTRY(transfer_to_handler)
53
54	GOT_ENTRY(__init_end)
55	GOT_ENTRY(__bss_end)
56	GOT_ENTRY(__bss_start)
57	END_GOT
58
59/*
60 * r3 - 1st arg to board_init(): IMMP pointer
61 * r4 - 2nd arg to board_init(): boot flag
62 */
63	.text
64	.long	0x27051956		/* U-Boot Magic Number			*/
65	.globl	version_string
66version_string:
67	.ascii U_BOOT_VERSION_STRING, "\0"
68
69	. = EXC_OFF_SYS_RESET
70	.globl	_start
71_start:
72	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
73	mtspr	638, r3
74
75	/* Initialize machine status; enable machine check interrupt		*/
76	/*----------------------------------------------------------------------*/
77	li	r3, MSR_KERNEL		/* Set ME, RI flags */
78	mtmsr	r3
79	mtspr	SRR1, r3		/* Make SRR1 match MSR */
80
81	mfspr	r3, ICR			/* clear Interrupt Cause Register */
82
83	/* Initialize debug port registers					*/
84	/*----------------------------------------------------------------------*/
85	xor	r0, r0, r0		/* Clear R0 */
86	mtspr	LCTRL1, r0		/* Initialize debug port regs */
87	mtspr	LCTRL2, r0
88	mtspr	COUNTA, r0
89	mtspr	COUNTB, r0
90
91	/* Reset the caches							*/
92	/*----------------------------------------------------------------------*/
93
94	mfspr	r3, IC_CST		/* Clear error bits */
95	mfspr	r3, DC_CST
96
97	lis	r3, IDC_UNALL@h		/* Unlock all */
98	mtspr	IC_CST, r3
99	mtspr	DC_CST, r3
100
101	lis	r3, IDC_INVALL@h	/* Invalidate all */
102	mtspr	IC_CST, r3
103	mtspr	DC_CST, r3
104
105	lis	r3, IDC_DISABLE@h	/* Disable data cache */
106	mtspr	DC_CST, r3
107
108	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
109	mtspr	IC_CST, r3
110
111	/* invalidate all tlb's							*/
112	/*----------------------------------------------------------------------*/
113
114	tlbia
115	isync
116
117	/*
118	 * Calculate absolute address in FLASH and jump there
119	 *----------------------------------------------------------------------*/
120
121	lis	r3, CONFIG_SYS_MONITOR_BASE@h
122	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
123	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
124	mtlr	r3
125	blr
126
127in_flash:
128
129	/* initialize some SPRs that are hard to access from C			*/
130	/*----------------------------------------------------------------------*/
131
132	/*
133	 * Disable serialized ifetch and show cycles
134	 * (i.e. set processor to normal mode).
135	 * This is also a silicon bug workaround, see errata
136	 */
137
138	li	r2, 0x0007
139	mtspr	ICTRL, r2
140
141	/* Set up debug mode entry */
142
143	lis	r2, CONFIG_SYS_DER@h
144	ori	r2, r2, CONFIG_SYS_DER@l
145	mtspr	DER, r2
146
147	/* set up the stack in internal DPRAM */
148	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
149	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
150	addi	r1, r3, -8
151
152	bl	board_init_f_alloc_reserve
153	addi	r1, r3, -8
154
155	/* Zeroise the CPM dpram */
156	lis	r4, CONFIG_SYS_IMMR@h
157	ori	r4, r4, (0x2000 - 4)
158	li	r0, (0x2000 / 4)
159	mtctr	r0
160	li	r0, 0
1611:	stwu	r0, 4(r4)
162	bdnz	1b
163
164	bl	board_init_f_init_reserve
165
166	/* let the C-code set up the rest					*/
167	/*									*/
168	/* Be careful to keep code relocatable !				*/
169	/*----------------------------------------------------------------------*/
170
171	GET_GOT			/* initialize GOT access			*/
172
173	lis	r3, CONFIG_SYS_IMMR@h
174	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
175
176	bl	board_init_f	/* run 1st part of board init code (from Flash) */
177
178	/* NOTREACHED - board_init_f() does not return */
179
180
181	.globl	_start_of_vectors
182_start_of_vectors:
183
184/* Machine check */
185	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
186
187/* Data Storage exception.  "Never" generated on the 860. */
188	STD_EXCEPTION(0x300, DataStorage, UnknownException)
189
190/* Instruction Storage exception.  "Never" generated on the 860. */
191	STD_EXCEPTION(0x400, InstStorage, UnknownException)
192
193/* External Interrupt exception. */
194	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
195
196/* Alignment exception. */
197	. = 0x600
198Alignment:
199	EXCEPTION_PROLOG(SRR0, SRR1)
200	mfspr	r4,DAR
201	stw	r4,_DAR(r21)
202	mfspr	r5,DSISR
203	stw	r5,_DSISR(r21)
204	addi	r3,r1,STACK_FRAME_OVERHEAD
205	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
206
207/* Program check exception */
208	. = 0x700
209ProgramCheck:
210	EXCEPTION_PROLOG(SRR0, SRR1)
211	addi	r3,r1,STACK_FRAME_OVERHEAD
212	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
213		MSR_KERNEL, COPY_EE)
214
215	/* No FPU on MPC8xx.  This exception is not supposed to happen.
216	*/
217	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
218
219	/* I guess we could implement decrementer, and may have
220	 * to someday for timekeeping.
221	 */
222	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
223	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
224	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
225	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
226	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
227
228	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
229	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
230
231	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
232	 * for all unimplemented and illegal instructions.
233	 */
234	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
235
236	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
237	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
238	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
239	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
240
241	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
242	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
243	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
244	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
245	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
246	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
247	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
248
249	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
250	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
251	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
252	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
253
254
255	.globl	_end_of_vectors
256_end_of_vectors:
257
258
259	. = 0x2000
260
261/*
262 * This code finishes saving the registers to the exception frame
263 * and jumps to the appropriate handler for the exception.
264 * Register r21 is pointer into trap frame, r1 has new stack pointer.
265 */
266	.globl	transfer_to_handler
267transfer_to_handler:
268	stw	r22,_NIP(r21)
269	lis	r22,MSR_POW@h
270	andc	r23,r23,r22
271	stw	r23,_MSR(r21)
272	SAVE_GPR(7, r21)
273	SAVE_4GPRS(8, r21)
274	SAVE_8GPRS(12, r21)
275	SAVE_8GPRS(24, r21)
276	mflr	r23
277	andi.	r24,r23,0x3f00		/* get vector offset */
278	stw	r24,TRAP(r21)
279	li	r22,0
280	stw	r22,RESULT(r21)
281	mtspr	SPRG2,r22		/* r1 is now kernel sp */
282	lwz	r24,0(r23)		/* virtual address of handler */
283	lwz	r23,4(r23)		/* where to go when done */
284	mtspr	SRR0,r24
285	mtspr	SRR1,r20
286	mtlr	r23
287	SYNC
288	rfi				/* jump to handler, enable MMU */
289
290int_return:
291	mfmsr	r28			/* Disable interrupts */
292	li	r4,0
293	ori	r4,r4,MSR_EE
294	andc	r28,r28,r4
295	SYNC				/* Some chip revs need this... */
296	mtmsr	r28
297	SYNC
298	lwz	r2,_CTR(r1)
299	lwz	r0,_LINK(r1)
300	mtctr	r2
301	mtlr	r0
302	lwz	r2,_XER(r1)
303	lwz	r0,_CCR(r1)
304	mtspr	XER,r2
305	mtcrf	0xFF,r0
306	REST_10GPRS(3, r1)
307	REST_10GPRS(13, r1)
308	REST_8GPRS(23, r1)
309	REST_GPR(31, r1)
310	lwz	r2,_NIP(r1)		/* Restore environment */
311	lwz	r0,_MSR(r1)
312	mtspr	SRR0,r2
313	mtspr	SRR1,r0
314	lwz	r0,GPR0(r1)
315	lwz	r2,GPR2(r1)
316	lwz	r1,GPR1(r1)
317	SYNC
318	rfi
319
320/*------------------------------------------------------------------------------*/
321
322/*
323 * void relocate_code (addr_sp, gd, addr_moni)
324 *
325 * This "function" does not return, instead it continues in RAM
326 * after relocating the monitor code.
327 *
328 * r3 = dest
329 * r4 = src
330 * r5 = length in bytes
331 * r6 = cachelinesize
332 */
333	.globl	relocate_code
334relocate_code:
335	mr	r1,  r3		/* Set new stack pointer		*/
336	mr	r9,  r4		/* Save copy of Global Data pointer	*/
337	mr	r10, r5		/* Save copy of Destination Address	*/
338
339	GET_GOT
340	mr	r3,  r5				/* Destination Address	*/
341	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
342	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
343	lwz	r5, GOT(__init_end)
344	sub	r5, r5, r4
345	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
346
347	/*
348	 * Fix GOT pointer:
349	 *
350	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
351	 *
352	 * Offset:
353	 */
354	sub	r15, r10, r4
355
356	/* First our own GOT */
357	add	r12, r12, r15
358	/* then the one used by the C code */
359	add	r30, r30, r15
360
361	/*
362	 * Now relocate code
363	 */
364
365	cmplw	cr1,r3,r4
366	addi	r0,r5,3
367	srwi.	r0,r0,2
368	beq	cr1,4f		/* In place copy is not necessary	*/
369	beq	7f		/* Protect against 0 count		*/
370	mtctr	r0
371	bge	cr1,2f
372
373	la	r8,-4(r4)
374	la	r7,-4(r3)
3751:	lwzu	r0,4(r8)
376	stwu	r0,4(r7)
377	bdnz	1b
378	b	4f
379
3802:	slwi	r0,r0,2
381	add	r8,r4,r0
382	add	r7,r3,r0
3833:	lwzu	r0,-4(r8)
384	stwu	r0,-4(r7)
385	bdnz	3b
386
387/*
388 * Now flush the cache: note that we must start from a cache aligned
389 * address. Otherwise we might miss one cache line.
390 */
3914:	cmpwi	r6,0
392	add	r5,r3,r5
393	beq	7f		/* Always flush prefetch queue in any case */
394	subi	r0,r6,1
395	andc	r3,r3,r0
396	mr	r4,r3
3975:	dcbst	0,r4
398	add	r4,r4,r6
399	cmplw	r4,r5
400	blt	5b
401	sync			/* Wait for all dcbst to complete on bus */
402	mr	r4,r3
4036:	icbi	0,r4
404	add	r4,r4,r6
405	cmplw	r4,r5
406	blt	6b
4077:	sync			/* Wait for all icbi to complete on bus	*/
408	isync
409
410/*
411 * We are done. Do not return, instead branch to second part of board
412 * initialization, now running from RAM.
413 */
414
415	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
416	mtlr	r0
417	blr
418
419in_ram:
420
421	/*
422	 * Relocation Function, r12 point to got2+0x8000
423	 *
424	 * Adjust got2 pointers, no need to check for 0, this code
425	 * already puts a few entries in the table.
426	 */
427	li	r0,__got2_entries@sectoff@l
428	la	r3,GOT(_GOT2_TABLE_)
429	lwz	r11,GOT(_GOT2_TABLE_)
430	mtctr	r0
431	sub	r11,r3,r11
432	addi	r3,r3,-4
4331:	lwzu	r0,4(r3)
434	cmpwi	r0,0
435	beq-	2f
436	add	r0,r0,r11
437	stw	r0,0(r3)
4382:	bdnz	1b
439
440	/*
441	 * Now adjust the fixups and the pointers to the fixups
442	 * in case we need to move ourselves again.
443	 */
444	li	r0,__fixup_entries@sectoff@l
445	lwz	r3,GOT(_FIXUP_TABLE_)
446	cmpwi	r0,0
447	mtctr	r0
448	addi	r3,r3,-4
449	beq	4f
4503:	lwzu	r4,4(r3)
451	lwzux	r0,r4,r11
452	cmpwi	r0,0
453	add	r0,r0,r11
454	stw	r4,0(r3)
455	beq-	5f
456	stw	r0,0(r4)
4575:	bdnz	3b
4584:
459clear_bss:
460	/*
461	 * Now clear BSS segment
462	 */
463	lwz	r3,GOT(__bss_start)
464	lwz	r4,GOT(__bss_end)
465
466	cmplw	0, r3, r4
467	beq	6f
468
469	li	r0, 0
4705:
471	stw	r0, 0(r3)
472	addi	r3, r3, 4
473	cmplw	0, r3, r4
474	bne	5b
4756:
476
477	mr	r3, r9		/* Global Data pointer		*/
478	mr	r4, r10		/* Destination Address		*/
479	bl	board_init_r
480
481	/*
482	 * Copy exception vector code to low memory
483	 *
484	 * r3: dest_addr
485	 * r7: source address, r8: end address, r9: target address
486	 */
487	.globl	trap_init
488trap_init:
489	mflr	r4			/* save link register		*/
490	GET_GOT
491	lwz	r7, GOT(_start)
492	lwz	r8, GOT(_end_of_vectors)
493
494	li	r9, 0x100		/* reset vector always at 0x100 */
495
496	cmplw	0, r7, r8
497	bgelr				/* return if r7>=r8 - just in case */
4981:
499	lwz	r0, 0(r7)
500	stw	r0, 0(r9)
501	addi	r7, r7, 4
502	addi	r9, r9, 4
503	cmplw	0, r7, r8
504	bne	1b
505
506	/*
507	 * relocate `hdlr' and `int_return' entries
508	 */
509	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
510	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
5112:
512	bl	trap_reloc
513	addi	r7, r7, 0x100		/* next exception vector	*/
514	cmplw	0, r7, r8
515	blt	2b
516
517	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
518	bl	trap_reloc
519
520	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
521	bl	trap_reloc
522
523	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
524	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
5253:
526	bl	trap_reloc
527	addi	r7, r7, 0x100		/* next exception vector	*/
528	cmplw	0, r7, r8
529	blt	3b
530
531	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
532	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5334:
534	bl	trap_reloc
535	addi	r7, r7, 0x100		/* next exception vector	*/
536	cmplw	0, r7, r8
537	blt	4b
538
539	mtlr	r4			/* restore link register	*/
540	blr
541