xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision ad5b5801) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#include <asm/cache.h>
33#include <asm/mmu.h>
34#include <asm/u-boot.h>
35
36/* We don't want the  MMU yet.
37*/
38#undef	MSR_KERNEL
39#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
40
41/*
42 * Set up GOT: Global Offset Table
43 *
44 * Use r12 to access the GOT
45 */
46	START_GOT
47	GOT_ENTRY(_GOT2_TABLE_)
48	GOT_ENTRY(_FIXUP_TABLE_)
49
50	GOT_ENTRY(_start)
51	GOT_ENTRY(_start_of_vectors)
52	GOT_ENTRY(_end_of_vectors)
53	GOT_ENTRY(transfer_to_handler)
54
55	GOT_ENTRY(__init_end)
56	GOT_ENTRY(__bss_end)
57	GOT_ENTRY(__bss_start)
58	END_GOT
59
60/*
61 * r3 - 1st arg to board_init(): IMMP pointer
62 * r4 - 2nd arg to board_init(): boot flag
63 */
64	.text
65	.long	0x27051956		/* U-Boot Magic Number			*/
66	.globl	version_string
67version_string:
68	.ascii U_BOOT_VERSION_STRING, "\0"
69
70	. = EXC_OFF_SYS_RESET
71	.globl	_start
72_start:
73	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
74	mtspr	638, r3
75
76	/* Initialize machine status; enable machine check interrupt		*/
77	/*----------------------------------------------------------------------*/
78	li	r3, MSR_KERNEL		/* Set ME, RI flags */
79	mtmsr	r3
80	mtspr	SRR1, r3		/* Make SRR1 match MSR */
81
82	mfspr	r3, ICR			/* clear Interrupt Cause Register */
83
84	/* Initialize debug port registers					*/
85	/*----------------------------------------------------------------------*/
86	xor	r0, r0, r0		/* Clear R0 */
87	mtspr	LCTRL1, r0		/* Initialize debug port regs */
88	mtspr	LCTRL2, r0
89	mtspr	COUNTA, r0
90	mtspr	COUNTB, r0
91
92	/* Reset the caches							*/
93	/*----------------------------------------------------------------------*/
94
95	mfspr	r3, IC_CST		/* Clear error bits */
96	mfspr	r3, DC_CST
97
98	lis	r3, IDC_UNALL@h		/* Unlock all */
99	mtspr	IC_CST, r3
100	mtspr	DC_CST, r3
101
102	lis	r3, IDC_INVALL@h	/* Invalidate all */
103	mtspr	IC_CST, r3
104	mtspr	DC_CST, r3
105
106	lis	r3, IDC_DISABLE@h	/* Disable data cache */
107	mtspr	DC_CST, r3
108
109#if !defined(CONFIG_SYS_DELAYED_ICACHE)
110					/* On IP860 and PCU E,
111					 * we cannot enable IC yet
112					 */
113	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
114#endif
115	mtspr	IC_CST, r3
116
117	/* invalidate all tlb's							*/
118	/*----------------------------------------------------------------------*/
119
120	tlbia
121	isync
122
123	/*
124	 * Calculate absolute address in FLASH and jump there
125	 *----------------------------------------------------------------------*/
126
127	lis	r3, CONFIG_SYS_MONITOR_BASE@h
128	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
129	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
130	mtlr	r3
131	blr
132
133in_flash:
134
135	/* initialize some SPRs that are hard to access from C			*/
136	/*----------------------------------------------------------------------*/
137
138	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
139	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
140	/* Note: R0 is still 0 here */
141	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
142	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
143
144	/*
145	 * Disable serialized ifetch and show cycles
146	 * (i.e. set processor to normal mode).
147	 * This is also a silicon bug workaround, see errata
148	 */
149
150	li	r2, 0x0007
151	mtspr	ICTRL, r2
152
153	/* Set up debug mode entry */
154
155	lis	r2, CONFIG_SYS_DER@h
156	ori	r2, r2, CONFIG_SYS_DER@l
157	mtspr	DER, r2
158
159	/* let the C-code set up the rest					*/
160	/*									*/
161	/* Be careful to keep code relocatable !				*/
162	/*----------------------------------------------------------------------*/
163
164	GET_GOT			/* initialize GOT access			*/
165
166	/* r3: IMMR */
167	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
168
169	bl	board_init_f	/* run 1st part of board init code (from Flash) */
170
171	/* NOTREACHED - board_init_f() does not return */
172
173
174	.globl	_start_of_vectors
175_start_of_vectors:
176
177/* Machine check */
178	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
179
180/* Data Storage exception.  "Never" generated on the 860. */
181	STD_EXCEPTION(0x300, DataStorage, UnknownException)
182
183/* Instruction Storage exception.  "Never" generated on the 860. */
184	STD_EXCEPTION(0x400, InstStorage, UnknownException)
185
186/* External Interrupt exception. */
187	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
188
189/* Alignment exception. */
190	. = 0x600
191Alignment:
192	EXCEPTION_PROLOG(SRR0, SRR1)
193	mfspr	r4,DAR
194	stw	r4,_DAR(r21)
195	mfspr	r5,DSISR
196	stw	r5,_DSISR(r21)
197	addi	r3,r1,STACK_FRAME_OVERHEAD
198	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
199
200/* Program check exception */
201	. = 0x700
202ProgramCheck:
203	EXCEPTION_PROLOG(SRR0, SRR1)
204	addi	r3,r1,STACK_FRAME_OVERHEAD
205	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
206		MSR_KERNEL, COPY_EE)
207
208	/* No FPU on MPC8xx.  This exception is not supposed to happen.
209	*/
210	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
211
212	/* I guess we could implement decrementer, and may have
213	 * to someday for timekeeping.
214	 */
215	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
216	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
217	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
218	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
219	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
220
221	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
222	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
223
224	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
225	 * for all unimplemented and illegal instructions.
226	 */
227	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
228
229	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
230	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
231	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
232	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
233
234	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
235	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
236	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
237	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
238	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
239	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
240	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
241
242	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
243	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
244	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
245	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
246
247
248	.globl	_end_of_vectors
249_end_of_vectors:
250
251
252	. = 0x2000
253
254/*
255 * This code finishes saving the registers to the exception frame
256 * and jumps to the appropriate handler for the exception.
257 * Register r21 is pointer into trap frame, r1 has new stack pointer.
258 */
259	.globl	transfer_to_handler
260transfer_to_handler:
261	stw	r22,_NIP(r21)
262	lis	r22,MSR_POW@h
263	andc	r23,r23,r22
264	stw	r23,_MSR(r21)
265	SAVE_GPR(7, r21)
266	SAVE_4GPRS(8, r21)
267	SAVE_8GPRS(12, r21)
268	SAVE_8GPRS(24, r21)
269	mflr	r23
270	andi.	r24,r23,0x3f00		/* get vector offset */
271	stw	r24,TRAP(r21)
272	li	r22,0
273	stw	r22,RESULT(r21)
274	mtspr	SPRG2,r22		/* r1 is now kernel sp */
275	lwz	r24,0(r23)		/* virtual address of handler */
276	lwz	r23,4(r23)		/* where to go when done */
277	mtspr	SRR0,r24
278	mtspr	SRR1,r20
279	mtlr	r23
280	SYNC
281	rfi				/* jump to handler, enable MMU */
282
283int_return:
284	mfmsr	r28			/* Disable interrupts */
285	li	r4,0
286	ori	r4,r4,MSR_EE
287	andc	r28,r28,r4
288	SYNC				/* Some chip revs need this... */
289	mtmsr	r28
290	SYNC
291	lwz	r2,_CTR(r1)
292	lwz	r0,_LINK(r1)
293	mtctr	r2
294	mtlr	r0
295	lwz	r2,_XER(r1)
296	lwz	r0,_CCR(r1)
297	mtspr	XER,r2
298	mtcrf	0xFF,r0
299	REST_10GPRS(3, r1)
300	REST_10GPRS(13, r1)
301	REST_8GPRS(23, r1)
302	REST_GPR(31, r1)
303	lwz	r2,_NIP(r1)		/* Restore environment */
304	lwz	r0,_MSR(r1)
305	mtspr	SRR0,r2
306	mtspr	SRR1,r0
307	lwz	r0,GPR0(r1)
308	lwz	r2,GPR2(r1)
309	lwz	r1,GPR1(r1)
310	SYNC
311	rfi
312
313/* Cache functions.
314*/
315	.globl	icache_enable
316icache_enable:
317	SYNC
318	lis	r3, IDC_INVALL@h
319	mtspr	IC_CST, r3
320	lis	r3, IDC_ENABLE@h
321	mtspr	IC_CST, r3
322	blr
323
324	.globl	icache_disable
325icache_disable:
326	SYNC
327	lis	r3, IDC_DISABLE@h
328	mtspr	IC_CST, r3
329	blr
330
331	.globl	icache_status
332icache_status:
333	mfspr	r3, IC_CST
334	srwi	r3, r3, 31	/* >>31 => select bit 0 */
335	blr
336
337	.globl	dcache_enable
338dcache_enable:
339#if 0
340	SYNC
341#endif
342#if 1
343	lis	r3, 0x0400		/* Set cache mode with MMU off */
344	mtspr	MD_CTR, r3
345#endif
346
347	lis	r3, IDC_INVALL@h
348	mtspr	DC_CST, r3
349#if 0
350	lis	r3, DC_SFWT@h
351	mtspr	DC_CST, r3
352#endif
353	lis	r3, IDC_ENABLE@h
354	mtspr	DC_CST, r3
355	blr
356
357	.globl	dcache_disable
358dcache_disable:
359	SYNC
360	lis	r3, IDC_DISABLE@h
361	mtspr	DC_CST, r3
362	lis	r3, IDC_INVALL@h
363	mtspr	DC_CST, r3
364	blr
365
366	.globl	dcache_status
367dcache_status:
368	mfspr	r3, DC_CST
369	srwi	r3, r3, 31	/* >>31 => select bit 0 */
370	blr
371
372	.globl	dc_read
373dc_read:
374	mtspr	DC_ADR, r3
375	mfspr	r3, DC_DAT
376	blr
377
378/*
379 * unsigned int get_immr (unsigned int mask)
380 *
381 * return (mask ? (IMMR & mask) : IMMR);
382 */
383	.globl	get_immr
384get_immr:
385	mr	r4,r3		/* save mask */
386	mfspr	r3, IMMR	/* IMMR */
387	cmpwi	0,r4,0		/* mask != 0 ? */
388	beq	4f
389	and	r3,r3,r4	/* IMMR & mask */
3904:
391	blr
392
393	.globl get_pvr
394get_pvr:
395	mfspr	r3, PVR
396	blr
397
398
399	.globl wr_ic_cst
400wr_ic_cst:
401	mtspr	IC_CST, r3
402	blr
403
404	.globl rd_ic_cst
405rd_ic_cst:
406	mfspr	r3, IC_CST
407	blr
408
409	.globl wr_ic_adr
410wr_ic_adr:
411	mtspr	IC_ADR, r3
412	blr
413
414
415	.globl wr_dc_cst
416wr_dc_cst:
417	mtspr	DC_CST, r3
418	blr
419
420	.globl rd_dc_cst
421rd_dc_cst:
422	mfspr	r3, DC_CST
423	blr
424
425	.globl wr_dc_adr
426wr_dc_adr:
427	mtspr	DC_ADR, r3
428	blr
429
430/*------------------------------------------------------------------------------*/
431
432/*
433 * void relocate_code (addr_sp, gd, addr_moni)
434 *
435 * This "function" does not return, instead it continues in RAM
436 * after relocating the monitor code.
437 *
438 * r3 = dest
439 * r4 = src
440 * r5 = length in bytes
441 * r6 = cachelinesize
442 */
443	.globl	relocate_code
444relocate_code:
445	mr	r1,  r3		/* Set new stack pointer		*/
446	mr	r9,  r4		/* Save copy of Global Data pointer	*/
447	mr	r10, r5		/* Save copy of Destination Address	*/
448
449	GET_GOT
450	mr	r3,  r5				/* Destination Address	*/
451	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
452	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
453	lwz	r5, GOT(__init_end)
454	sub	r5, r5, r4
455	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
456
457	/*
458	 * Fix GOT pointer:
459	 *
460	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
461	 *
462	 * Offset:
463	 */
464	sub	r15, r10, r4
465
466	/* First our own GOT */
467	add	r12, r12, r15
468	/* then the one used by the C code */
469	add	r30, r30, r15
470
471	/*
472	 * Now relocate code
473	 */
474
475	cmplw	cr1,r3,r4
476	addi	r0,r5,3
477	srwi.	r0,r0,2
478	beq	cr1,4f		/* In place copy is not necessary	*/
479	beq	7f		/* Protect against 0 count		*/
480	mtctr	r0
481	bge	cr1,2f
482
483	la	r8,-4(r4)
484	la	r7,-4(r3)
4851:	lwzu	r0,4(r8)
486	stwu	r0,4(r7)
487	bdnz	1b
488	b	4f
489
4902:	slwi	r0,r0,2
491	add	r8,r4,r0
492	add	r7,r3,r0
4933:	lwzu	r0,-4(r8)
494	stwu	r0,-4(r7)
495	bdnz	3b
496
497/*
498 * Now flush the cache: note that we must start from a cache aligned
499 * address. Otherwise we might miss one cache line.
500 */
5014:	cmpwi	r6,0
502	add	r5,r3,r5
503	beq	7f		/* Always flush prefetch queue in any case */
504	subi	r0,r6,1
505	andc	r3,r3,r0
506	mr	r4,r3
5075:	dcbst	0,r4
508	add	r4,r4,r6
509	cmplw	r4,r5
510	blt	5b
511	sync			/* Wait for all dcbst to complete on bus */
512	mr	r4,r3
5136:	icbi	0,r4
514	add	r4,r4,r6
515	cmplw	r4,r5
516	blt	6b
5177:	sync			/* Wait for all icbi to complete on bus	*/
518	isync
519
520/*
521 * We are done. Do not return, instead branch to second part of board
522 * initialization, now running from RAM.
523 */
524
525	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
526	mtlr	r0
527	blr
528
529in_ram:
530
531	/*
532	 * Relocation Function, r12 point to got2+0x8000
533	 *
534	 * Adjust got2 pointers, no need to check for 0, this code
535	 * already puts a few entries in the table.
536	 */
537	li	r0,__got2_entries@sectoff@l
538	la	r3,GOT(_GOT2_TABLE_)
539	lwz	r11,GOT(_GOT2_TABLE_)
540	mtctr	r0
541	sub	r11,r3,r11
542	addi	r3,r3,-4
5431:	lwzu	r0,4(r3)
544	cmpwi	r0,0
545	beq-	2f
546	add	r0,r0,r11
547	stw	r0,0(r3)
5482:	bdnz	1b
549
550	/*
551	 * Now adjust the fixups and the pointers to the fixups
552	 * in case we need to move ourselves again.
553	 */
554	li	r0,__fixup_entries@sectoff@l
555	lwz	r3,GOT(_FIXUP_TABLE_)
556	cmpwi	r0,0
557	mtctr	r0
558	addi	r3,r3,-4
559	beq	4f
5603:	lwzu	r4,4(r3)
561	lwzux	r0,r4,r11
562	cmpwi	r0,0
563	add	r0,r0,r11
564	stw	r4,0(r3)
565	beq-	5f
566	stw	r0,0(r4)
5675:	bdnz	3b
5684:
569clear_bss:
570	/*
571	 * Now clear BSS segment
572	 */
573	lwz	r3,GOT(__bss_start)
574	lwz	r4,GOT(__bss_end)
575
576	cmplw	0, r3, r4
577	beq	6f
578
579	li	r0, 0
5805:
581	stw	r0, 0(r3)
582	addi	r3, r3, 4
583	cmplw	0, r3, r4
584	bne	5b
5856:
586
587	mr	r3, r9		/* Global Data pointer		*/
588	mr	r4, r10		/* Destination Address		*/
589	bl	board_init_r
590
591	/*
592	 * Copy exception vector code to low memory
593	 *
594	 * r3: dest_addr
595	 * r7: source address, r8: end address, r9: target address
596	 */
597	.globl	trap_init
598trap_init:
599	mflr	r4			/* save link register		*/
600	GET_GOT
601	lwz	r7, GOT(_start)
602	lwz	r8, GOT(_end_of_vectors)
603
604	li	r9, 0x100		/* reset vector always at 0x100 */
605
606	cmplw	0, r7, r8
607	bgelr				/* return if r7>=r8 - just in case */
6081:
609	lwz	r0, 0(r7)
610	stw	r0, 0(r9)
611	addi	r7, r7, 4
612	addi	r9, r9, 4
613	cmplw	0, r7, r8
614	bne	1b
615
616	/*
617	 * relocate `hdlr' and `int_return' entries
618	 */
619	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
620	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6212:
622	bl	trap_reloc
623	addi	r7, r7, 0x100		/* next exception vector	*/
624	cmplw	0, r7, r8
625	blt	2b
626
627	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
628	bl	trap_reloc
629
630	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
631	bl	trap_reloc
632
633	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
634	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6353:
636	bl	trap_reloc
637	addi	r7, r7, 0x100		/* next exception vector	*/
638	cmplw	0, r7, r8
639	blt	3b
640
641	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
642	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6434:
644	bl	trap_reloc
645	addi	r7, r7, 0x100		/* next exception vector	*/
646	cmplw	0, r7, r8
647	blt	4b
648
649	mtlr	r4			/* restore link register	*/
650	blr
651