xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision 54841ab5) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*  U-Boot - Startup Code for PowerPC based Embedded Boards
26 *
27 *
28 *  The processor starts at 0x00000100 and the code is executed
29 *  from flash. The code is organized to be at an other address
30 *  in memory, but as long we don't jump around before relocating,
31 *  board_init lies at a quite high address and when the cpu has
32 *  jumped there, everything is ok.
33 *  This works because the cpu gives the FLASH (CS0) the whole
34 *  address space at startup, and board_init lies as a echo of
35 *  the flash somewhere up there in the memory map.
36 *
37 *  board_init will change CS0 to be positioned at the correct
38 *  address and (s)dram will be positioned at address 0
39 */
40#include <config.h>
41#include <mpc8xx.h>
42#include <timestamp.h>
43#include <version.h>
44
45#define CONFIG_8xx 1		/* needed for Linux kernel header files */
46#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
47
48#include <ppc_asm.tmpl>
49#include <ppc_defs.h>
50
51#include <asm/cache.h>
52#include <asm/mmu.h>
53
54#ifndef  CONFIG_IDENT_STRING
55#define  CONFIG_IDENT_STRING ""
56#endif
57
58/* We don't want the  MMU yet.
59*/
60#undef	MSR_KERNEL
61#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
62
63/*
64 * Set up GOT: Global Offset Table
65 *
66 * Use r12 to access the GOT
67 */
68	START_GOT
69	GOT_ENTRY(_GOT2_TABLE_)
70	GOT_ENTRY(_FIXUP_TABLE_)
71
72	GOT_ENTRY(_start)
73	GOT_ENTRY(_start_of_vectors)
74	GOT_ENTRY(_end_of_vectors)
75	GOT_ENTRY(transfer_to_handler)
76
77	GOT_ENTRY(__init_end)
78	GOT_ENTRY(_end)
79	GOT_ENTRY(__bss_start)
80	END_GOT
81
82/*
83 * r3 - 1st arg to board_init(): IMMP pointer
84 * r4 - 2nd arg to board_init(): boot flag
85 */
86	.text
87	.long	0x27051956		/* U-Boot Magic Number			*/
88	.globl	version_string
89version_string:
90	.ascii U_BOOT_VERSION
91	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
92	.ascii CONFIG_IDENT_STRING, "\0"
93
94	. = EXC_OFF_SYS_RESET
95	.globl	_start
96_start:
97	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
98	mtspr	638, r3
99	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
100	b	boot_cold
101
102	. = EXC_OFF_SYS_RESET + 0x10
103
104	.globl	_start_warm
105_start_warm:
106	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
107	b	boot_warm
108
109boot_cold:
110boot_warm:
111
112	/* Initialize machine status; enable machine check interrupt		*/
113	/*----------------------------------------------------------------------*/
114	li	r3, MSR_KERNEL		/* Set ME, RI flags */
115	mtmsr	r3
116	mtspr	SRR1, r3		/* Make SRR1 match MSR */
117
118	mfspr	r3, ICR			/* clear Interrupt Cause Register */
119
120	/* Initialize debug port registers					*/
121	/*----------------------------------------------------------------------*/
122	xor	r0, r0, r0		/* Clear R0 */
123	mtspr	LCTRL1, r0		/* Initialize debug port regs */
124	mtspr	LCTRL2, r0
125	mtspr	COUNTA, r0
126	mtspr	COUNTB, r0
127
128	/* Reset the caches							*/
129	/*----------------------------------------------------------------------*/
130
131	mfspr	r3, IC_CST		/* Clear error bits */
132	mfspr	r3, DC_CST
133
134	lis	r3, IDC_UNALL@h		/* Unlock all */
135	mtspr	IC_CST, r3
136	mtspr	DC_CST, r3
137
138	lis	r3, IDC_INVALL@h	/* Invalidate all */
139	mtspr	IC_CST, r3
140	mtspr	DC_CST, r3
141
142	lis	r3, IDC_DISABLE@h	/* Disable data cache */
143	mtspr	DC_CST, r3
144
145#if !defined(CONFIG_SYS_DELAYED_ICACHE)
146					/* On IP860 and PCU E,
147					 * we cannot enable IC yet
148					 */
149	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
150#endif
151	mtspr	IC_CST, r3
152
153	/* invalidate all tlb's							*/
154	/*----------------------------------------------------------------------*/
155
156	tlbia
157	isync
158
159	/*
160	 * Calculate absolute address in FLASH and jump there
161	 *----------------------------------------------------------------------*/
162
163	lis	r3, CONFIG_SYS_MONITOR_BASE@h
164	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
165	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
166	mtlr	r3
167	blr
168
169in_flash:
170
171	/* initialize some SPRs that are hard to access from C			*/
172	/*----------------------------------------------------------------------*/
173
174	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
175	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
176	/* Note: R0 is still 0 here */
177	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
178	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
179
180	/*
181	 * Disable serialized ifetch and show cycles
182	 * (i.e. set processor to normal mode).
183	 * This is also a silicon bug workaround, see errata
184	 */
185
186	li	r2, 0x0007
187	mtspr	ICTRL, r2
188
189	/* Set up debug mode entry */
190
191	lis	r2, CONFIG_SYS_DER@h
192	ori	r2, r2, CONFIG_SYS_DER@l
193	mtspr	DER, r2
194
195	/* let the C-code set up the rest					*/
196	/*									*/
197	/* Be careful to keep code relocatable !				*/
198	/*----------------------------------------------------------------------*/
199
200	GET_GOT			/* initialize GOT access			*/
201
202	/* r3: IMMR */
203	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
204
205	mr	r3, r21
206	/* r3: BOOTFLAG */
207	bl	board_init_f	/* run 1st part of board init code (from Flash) */
208
209
210	.globl	_start_of_vectors
211_start_of_vectors:
212
213/* Machine check */
214	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
215
216/* Data Storage exception.  "Never" generated on the 860. */
217	STD_EXCEPTION(0x300, DataStorage, UnknownException)
218
219/* Instruction Storage exception.  "Never" generated on the 860. */
220	STD_EXCEPTION(0x400, InstStorage, UnknownException)
221
222/* External Interrupt exception. */
223	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
224
225/* Alignment exception. */
226	. = 0x600
227Alignment:
228	EXCEPTION_PROLOG(SRR0, SRR1)
229	mfspr	r4,DAR
230	stw	r4,_DAR(r21)
231	mfspr	r5,DSISR
232	stw	r5,_DSISR(r21)
233	addi	r3,r1,STACK_FRAME_OVERHEAD
234	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
235
236/* Program check exception */
237	. = 0x700
238ProgramCheck:
239	EXCEPTION_PROLOG(SRR0, SRR1)
240	addi	r3,r1,STACK_FRAME_OVERHEAD
241	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
242		MSR_KERNEL, COPY_EE)
243
244	/* No FPU on MPC8xx.  This exception is not supposed to happen.
245	*/
246	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
247
248	/* I guess we could implement decrementer, and may have
249	 * to someday for timekeeping.
250	 */
251	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
252	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
253	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
254	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
255	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
256
257	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
258	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
259
260	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
261	 * for all unimplemented and illegal instructions.
262	 */
263	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
264
265	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
266	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
267	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
268	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
269
270	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
271	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
272	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
273	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
274	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
275	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
276	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
277
278	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
279	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
280	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
281	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
282
283
284	.globl	_end_of_vectors
285_end_of_vectors:
286
287
288	. = 0x2000
289
290/*
291 * This code finishes saving the registers to the exception frame
292 * and jumps to the appropriate handler for the exception.
293 * Register r21 is pointer into trap frame, r1 has new stack pointer.
294 */
295	.globl	transfer_to_handler
296transfer_to_handler:
297	stw	r22,_NIP(r21)
298	lis	r22,MSR_POW@h
299	andc	r23,r23,r22
300	stw	r23,_MSR(r21)
301	SAVE_GPR(7, r21)
302	SAVE_4GPRS(8, r21)
303	SAVE_8GPRS(12, r21)
304	SAVE_8GPRS(24, r21)
305	mflr	r23
306	andi.	r24,r23,0x3f00		/* get vector offset */
307	stw	r24,TRAP(r21)
308	li	r22,0
309	stw	r22,RESULT(r21)
310	mtspr	SPRG2,r22		/* r1 is now kernel sp */
311	lwz	r24,0(r23)		/* virtual address of handler */
312	lwz	r23,4(r23)		/* where to go when done */
313	mtspr	SRR0,r24
314	mtspr	SRR1,r20
315	mtlr	r23
316	SYNC
317	rfi				/* jump to handler, enable MMU */
318
319int_return:
320	mfmsr	r28			/* Disable interrupts */
321	li	r4,0
322	ori	r4,r4,MSR_EE
323	andc	r28,r28,r4
324	SYNC				/* Some chip revs need this... */
325	mtmsr	r28
326	SYNC
327	lwz	r2,_CTR(r1)
328	lwz	r0,_LINK(r1)
329	mtctr	r2
330	mtlr	r0
331	lwz	r2,_XER(r1)
332	lwz	r0,_CCR(r1)
333	mtspr	XER,r2
334	mtcrf	0xFF,r0
335	REST_10GPRS(3, r1)
336	REST_10GPRS(13, r1)
337	REST_8GPRS(23, r1)
338	REST_GPR(31, r1)
339	lwz	r2,_NIP(r1)		/* Restore environment */
340	lwz	r0,_MSR(r1)
341	mtspr	SRR0,r2
342	mtspr	SRR1,r0
343	lwz	r0,GPR0(r1)
344	lwz	r2,GPR2(r1)
345	lwz	r1,GPR1(r1)
346	SYNC
347	rfi
348
349/* Cache functions.
350*/
351	.globl	icache_enable
352icache_enable:
353	SYNC
354	lis	r3, IDC_INVALL@h
355	mtspr	IC_CST, r3
356	lis	r3, IDC_ENABLE@h
357	mtspr	IC_CST, r3
358	blr
359
360	.globl	icache_disable
361icache_disable:
362	SYNC
363	lis	r3, IDC_DISABLE@h
364	mtspr	IC_CST, r3
365	blr
366
367	.globl	icache_status
368icache_status:
369	mfspr	r3, IC_CST
370	srwi	r3, r3, 31	/* >>31 => select bit 0 */
371	blr
372
373	.globl	dcache_enable
374dcache_enable:
375#if 0
376	SYNC
377#endif
378#if 1
379	lis	r3, 0x0400		/* Set cache mode with MMU off */
380	mtspr	MD_CTR, r3
381#endif
382
383	lis	r3, IDC_INVALL@h
384	mtspr	DC_CST, r3
385#if 0
386	lis	r3, DC_SFWT@h
387	mtspr	DC_CST, r3
388#endif
389	lis	r3, IDC_ENABLE@h
390	mtspr	DC_CST, r3
391	blr
392
393	.globl	dcache_disable
394dcache_disable:
395	SYNC
396	lis	r3, IDC_DISABLE@h
397	mtspr	DC_CST, r3
398	lis	r3, IDC_INVALL@h
399	mtspr	DC_CST, r3
400	blr
401
402	.globl	dcache_status
403dcache_status:
404	mfspr	r3, DC_CST
405	srwi	r3, r3, 31	/* >>31 => select bit 0 */
406	blr
407
408	.globl	dc_read
409dc_read:
410	mtspr	DC_ADR, r3
411	mfspr	r3, DC_DAT
412	blr
413
414/*
415 * unsigned int get_immr (unsigned int mask)
416 *
417 * return (mask ? (IMMR & mask) : IMMR);
418 */
419	.globl	get_immr
420get_immr:
421	mr	r4,r3		/* save mask */
422	mfspr	r3, IMMR	/* IMMR */
423	cmpwi	0,r4,0		/* mask != 0 ? */
424	beq	4f
425	and	r3,r3,r4	/* IMMR & mask */
4264:
427	blr
428
429	.globl get_pvr
430get_pvr:
431	mfspr	r3, PVR
432	blr
433
434
435	.globl wr_ic_cst
436wr_ic_cst:
437	mtspr	IC_CST, r3
438	blr
439
440	.globl rd_ic_cst
441rd_ic_cst:
442	mfspr	r3, IC_CST
443	blr
444
445	.globl wr_ic_adr
446wr_ic_adr:
447	mtspr	IC_ADR, r3
448	blr
449
450
451	.globl wr_dc_cst
452wr_dc_cst:
453	mtspr	DC_CST, r3
454	blr
455
456	.globl rd_dc_cst
457rd_dc_cst:
458	mfspr	r3, DC_CST
459	blr
460
461	.globl wr_dc_adr
462wr_dc_adr:
463	mtspr	DC_ADR, r3
464	blr
465
466/*------------------------------------------------------------------------------*/
467
468/*
469 * void relocate_code (addr_sp, gd, addr_moni)
470 *
471 * This "function" does not return, instead it continues in RAM
472 * after relocating the monitor code.
473 *
474 * r3 = dest
475 * r4 = src
476 * r5 = length in bytes
477 * r6 = cachelinesize
478 */
479	.globl	relocate_code
480relocate_code:
481	mr	r1,  r3		/* Set new stack pointer		*/
482	mr	r9,  r4		/* Save copy of Global Data pointer	*/
483	mr	r10, r5		/* Save copy of Destination Address	*/
484
485	GET_GOT
486	mr	r3,  r5				/* Destination Address	*/
487	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
488	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
489	lwz	r5, GOT(__init_end)
490	sub	r5, r5, r4
491	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
492
493	/*
494	 * Fix GOT pointer:
495	 *
496	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
497	 *
498	 * Offset:
499	 */
500	sub	r15, r10, r4
501
502	/* First our own GOT */
503	add	r12, r12, r15
504	/* then the one used by the C code */
505	add	r30, r30, r15
506
507	/*
508	 * Now relocate code
509	 */
510
511	cmplw	cr1,r3,r4
512	addi	r0,r5,3
513	srwi.	r0,r0,2
514	beq	cr1,4f		/* In place copy is not necessary	*/
515	beq	7f		/* Protect against 0 count		*/
516	mtctr	r0
517	bge	cr1,2f
518
519	la	r8,-4(r4)
520	la	r7,-4(r3)
5211:	lwzu	r0,4(r8)
522	stwu	r0,4(r7)
523	bdnz	1b
524	b	4f
525
5262:	slwi	r0,r0,2
527	add	r8,r4,r0
528	add	r7,r3,r0
5293:	lwzu	r0,-4(r8)
530	stwu	r0,-4(r7)
531	bdnz	3b
532
533/*
534 * Now flush the cache: note that we must start from a cache aligned
535 * address. Otherwise we might miss one cache line.
536 */
5374:	cmpwi	r6,0
538	add	r5,r3,r5
539	beq	7f		/* Always flush prefetch queue in any case */
540	subi	r0,r6,1
541	andc	r3,r3,r0
542	mr	r4,r3
5435:	dcbst	0,r4
544	add	r4,r4,r6
545	cmplw	r4,r5
546	blt	5b
547	sync			/* Wait for all dcbst to complete on bus */
548	mr	r4,r3
5496:	icbi	0,r4
550	add	r4,r4,r6
551	cmplw	r4,r5
552	blt	6b
5537:	sync			/* Wait for all icbi to complete on bus	*/
554	isync
555
556/*
557 * We are done. Do not return, instead branch to second part of board
558 * initialization, now running from RAM.
559 */
560
561	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
562	mtlr	r0
563	blr
564
565in_ram:
566
567	/*
568	 * Relocation Function, r12 point to got2+0x8000
569	 *
570	 * Adjust got2 pointers, no need to check for 0, this code
571	 * already puts a few entries in the table.
572	 */
573	li	r0,__got2_entries@sectoff@l
574	la	r3,GOT(_GOT2_TABLE_)
575	lwz	r11,GOT(_GOT2_TABLE_)
576	mtctr	r0
577	sub	r11,r3,r11
578	addi	r3,r3,-4
5791:	lwzu	r0,4(r3)
580	cmpwi	r0,0
581	beq-	2f
582	add	r0,r0,r11
583	stw	r0,0(r3)
5842:	bdnz	1b
585
586	/*
587	 * Now adjust the fixups and the pointers to the fixups
588	 * in case we need to move ourselves again.
589	 */
590	li	r0,__fixup_entries@sectoff@l
591	lwz	r3,GOT(_FIXUP_TABLE_)
592	cmpwi	r0,0
593	mtctr	r0
594	addi	r3,r3,-4
595	beq	4f
5963:	lwzu	r4,4(r3)
597	lwzux	r0,r4,r11
598	add	r0,r0,r11
599	stw	r10,0(r3)
600	stw	r0,0(r4)
601	bdnz	3b
6024:
603clear_bss:
604	/*
605	 * Now clear BSS segment
606	 */
607	lwz	r3,GOT(__bss_start)
608	lwz	r4,GOT(_end)
609
610	cmplw	0, r3, r4
611	beq	6f
612
613	li	r0, 0
6145:
615	stw	r0, 0(r3)
616	addi	r3, r3, 4
617	cmplw	0, r3, r4
618	bne	5b
6196:
620
621	mr	r3, r9		/* Global Data pointer		*/
622	mr	r4, r10		/* Destination Address		*/
623	bl	board_init_r
624
625	/*
626	 * Copy exception vector code to low memory
627	 *
628	 * r3: dest_addr
629	 * r7: source address, r8: end address, r9: target address
630	 */
631	.globl	trap_init
632trap_init:
633	mflr	r4			/* save link register		*/
634	GET_GOT
635	lwz	r7, GOT(_start)
636	lwz	r8, GOT(_end_of_vectors)
637
638	li	r9, 0x100		/* reset vector always at 0x100 */
639
640	cmplw	0, r7, r8
641	bgelr				/* return if r7>=r8 - just in case */
6421:
643	lwz	r0, 0(r7)
644	stw	r0, 0(r9)
645	addi	r7, r7, 4
646	addi	r9, r9, 4
647	cmplw	0, r7, r8
648	bne	1b
649
650	/*
651	 * relocate `hdlr' and `int_return' entries
652	 */
653	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
654	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6552:
656	bl	trap_reloc
657	addi	r7, r7, 0x100		/* next exception vector	*/
658	cmplw	0, r7, r8
659	blt	2b
660
661	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
662	bl	trap_reloc
663
664	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
665	bl	trap_reloc
666
667	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
668	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6693:
670	bl	trap_reloc
671	addi	r7, r7, 0x100		/* next exception vector	*/
672	cmplw	0, r7, r8
673	blt	3b
674
675	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
676	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6774:
678	bl	trap_reloc
679	addi	r7, r7, 0x100		/* next exception vector	*/
680	cmplw	0, r7, r8
681	blt	4b
682
683	mtlr	r4			/* restore link register	*/
684	blr
685