xref: /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/start.S (revision 2ecba112) 
1/*
2 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
3 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/*  U-Boot - Startup Code for PowerPC based Embedded Boards
10 *
11 *
12 *  The processor starts at 0x00000100 and the code is executed
13 *  from flash. The code is organized to be at an other address
14 *  in memory, but as long we don't jump around before relocating,
15 *  board_init lies at a quite high address and when the cpu has
16 *  jumped there, everything is ok.
17 *  This works because the cpu gives the FLASH (CS0) the whole
18 *  address space at startup, and board_init lies as a echo of
19 *  the flash somewhere up there in the memory map.
20 *
21 *  board_init will change CS0 to be positioned at the correct
22 *  address and (s)dram will be positioned at address 0
23 */
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include <version.h>
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#include <asm/cache.h>
33#include <asm/mmu.h>
34#include <asm/u-boot.h>
35
36/* We don't want the  MMU yet.
37*/
38#undef	MSR_KERNEL
39#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
40
41/*
42 * Set up GOT: Global Offset Table
43 *
44 * Use r12 to access the GOT
45 */
46	START_GOT
47	GOT_ENTRY(_GOT2_TABLE_)
48	GOT_ENTRY(_FIXUP_TABLE_)
49
50	GOT_ENTRY(_start)
51	GOT_ENTRY(_start_of_vectors)
52	GOT_ENTRY(_end_of_vectors)
53	GOT_ENTRY(transfer_to_handler)
54
55	GOT_ENTRY(__init_end)
56	GOT_ENTRY(__bss_end)
57	GOT_ENTRY(__bss_start)
58	END_GOT
59
60/*
61 * r3 - 1st arg to board_init(): IMMP pointer
62 * r4 - 2nd arg to board_init(): boot flag
63 */
64	.text
65	.long	0x27051956		/* U-Boot Magic Number			*/
66	.globl	version_string
67version_string:
68	.ascii U_BOOT_VERSION_STRING, "\0"
69
70	. = EXC_OFF_SYS_RESET
71	.globl	_start
72_start:
73	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
74	mtspr	638, r3
75
76	/* Initialize machine status; enable machine check interrupt		*/
77	/*----------------------------------------------------------------------*/
78	li	r3, MSR_KERNEL		/* Set ME, RI flags */
79	mtmsr	r3
80	mtspr	SRR1, r3		/* Make SRR1 match MSR */
81
82	mfspr	r3, ICR			/* clear Interrupt Cause Register */
83
84	/* Initialize debug port registers					*/
85	/*----------------------------------------------------------------------*/
86	xor	r0, r0, r0		/* Clear R0 */
87	mtspr	LCTRL1, r0		/* Initialize debug port regs */
88	mtspr	LCTRL2, r0
89	mtspr	COUNTA, r0
90	mtspr	COUNTB, r0
91
92	/* Reset the caches							*/
93	/*----------------------------------------------------------------------*/
94
95	mfspr	r3, IC_CST		/* Clear error bits */
96	mfspr	r3, DC_CST
97
98	lis	r3, IDC_UNALL@h		/* Unlock all */
99	mtspr	IC_CST, r3
100	mtspr	DC_CST, r3
101
102	lis	r3, IDC_INVALL@h	/* Invalidate all */
103	mtspr	IC_CST, r3
104	mtspr	DC_CST, r3
105
106	lis	r3, IDC_DISABLE@h	/* Disable data cache */
107	mtspr	DC_CST, r3
108
109	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
110	mtspr	IC_CST, r3
111
112	/* invalidate all tlb's							*/
113	/*----------------------------------------------------------------------*/
114
115	tlbia
116	isync
117
118	/*
119	 * Calculate absolute address in FLASH and jump there
120	 *----------------------------------------------------------------------*/
121
122	lis	r3, CONFIG_SYS_MONITOR_BASE@h
123	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
124	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
125	mtlr	r3
126	blr
127
128in_flash:
129
130	/* initialize some SPRs that are hard to access from C			*/
131	/*----------------------------------------------------------------------*/
132
133	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
134	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
135	/* Note: R0 is still 0 here */
136	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
137	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
138
139	/*
140	 * Disable serialized ifetch and show cycles
141	 * (i.e. set processor to normal mode).
142	 * This is also a silicon bug workaround, see errata
143	 */
144
145	li	r2, 0x0007
146	mtspr	ICTRL, r2
147
148	/* Set up debug mode entry */
149
150	lis	r2, CONFIG_SYS_DER@h
151	ori	r2, r2, CONFIG_SYS_DER@l
152	mtspr	DER, r2
153
154	/* let the C-code set up the rest					*/
155	/*									*/
156	/* Be careful to keep code relocatable !				*/
157	/*----------------------------------------------------------------------*/
158
159	GET_GOT			/* initialize GOT access			*/
160
161	/* r3: IMMR */
162	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
163
164	bl	board_init_f	/* run 1st part of board init code (from Flash) */
165
166	/* NOTREACHED - board_init_f() does not return */
167
168
169	.globl	_start_of_vectors
170_start_of_vectors:
171
172/* Machine check */
173	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
174
175/* Data Storage exception.  "Never" generated on the 860. */
176	STD_EXCEPTION(0x300, DataStorage, UnknownException)
177
178/* Instruction Storage exception.  "Never" generated on the 860. */
179	STD_EXCEPTION(0x400, InstStorage, UnknownException)
180
181/* External Interrupt exception. */
182	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
183
184/* Alignment exception. */
185	. = 0x600
186Alignment:
187	EXCEPTION_PROLOG(SRR0, SRR1)
188	mfspr	r4,DAR
189	stw	r4,_DAR(r21)
190	mfspr	r5,DSISR
191	stw	r5,_DSISR(r21)
192	addi	r3,r1,STACK_FRAME_OVERHEAD
193	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
194
195/* Program check exception */
196	. = 0x700
197ProgramCheck:
198	EXCEPTION_PROLOG(SRR0, SRR1)
199	addi	r3,r1,STACK_FRAME_OVERHEAD
200	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
201		MSR_KERNEL, COPY_EE)
202
203	/* No FPU on MPC8xx.  This exception is not supposed to happen.
204	*/
205	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
206
207	/* I guess we could implement decrementer, and may have
208	 * to someday for timekeeping.
209	 */
210	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
211	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
212	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
213	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
214	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
215
216	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
217	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
218
219	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
220	 * for all unimplemented and illegal instructions.
221	 */
222	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
223
224	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
225	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
226	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
227	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
228
229	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
230	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
231	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
232	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
233	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
234	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
235	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
236
237	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
238	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
239	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
240	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
241
242
243	.globl	_end_of_vectors
244_end_of_vectors:
245
246
247	. = 0x2000
248
249/*
250 * This code finishes saving the registers to the exception frame
251 * and jumps to the appropriate handler for the exception.
252 * Register r21 is pointer into trap frame, r1 has new stack pointer.
253 */
254	.globl	transfer_to_handler
255transfer_to_handler:
256	stw	r22,_NIP(r21)
257	lis	r22,MSR_POW@h
258	andc	r23,r23,r22
259	stw	r23,_MSR(r21)
260	SAVE_GPR(7, r21)
261	SAVE_4GPRS(8, r21)
262	SAVE_8GPRS(12, r21)
263	SAVE_8GPRS(24, r21)
264	mflr	r23
265	andi.	r24,r23,0x3f00		/* get vector offset */
266	stw	r24,TRAP(r21)
267	li	r22,0
268	stw	r22,RESULT(r21)
269	mtspr	SPRG2,r22		/* r1 is now kernel sp */
270	lwz	r24,0(r23)		/* virtual address of handler */
271	lwz	r23,4(r23)		/* where to go when done */
272	mtspr	SRR0,r24
273	mtspr	SRR1,r20
274	mtlr	r23
275	SYNC
276	rfi				/* jump to handler, enable MMU */
277
278int_return:
279	mfmsr	r28			/* Disable interrupts */
280	li	r4,0
281	ori	r4,r4,MSR_EE
282	andc	r28,r28,r4
283	SYNC				/* Some chip revs need this... */
284	mtmsr	r28
285	SYNC
286	lwz	r2,_CTR(r1)
287	lwz	r0,_LINK(r1)
288	mtctr	r2
289	mtlr	r0
290	lwz	r2,_XER(r1)
291	lwz	r0,_CCR(r1)
292	mtspr	XER,r2
293	mtcrf	0xFF,r0
294	REST_10GPRS(3, r1)
295	REST_10GPRS(13, r1)
296	REST_8GPRS(23, r1)
297	REST_GPR(31, r1)
298	lwz	r2,_NIP(r1)		/* Restore environment */
299	lwz	r0,_MSR(r1)
300	mtspr	SRR0,r2
301	mtspr	SRR1,r0
302	lwz	r0,GPR0(r1)
303	lwz	r2,GPR2(r1)
304	lwz	r1,GPR1(r1)
305	SYNC
306	rfi
307
308/* Cache functions.
309*/
310	.globl	icache_enable
311icache_enable:
312	SYNC
313	lis	r3, IDC_INVALL@h
314	mtspr	IC_CST, r3
315	lis	r3, IDC_ENABLE@h
316	mtspr	IC_CST, r3
317	blr
318
319	.globl	icache_disable
320icache_disable:
321	SYNC
322	lis	r3, IDC_DISABLE@h
323	mtspr	IC_CST, r3
324	blr
325
326	.globl	icache_status
327icache_status:
328	mfspr	r3, IC_CST
329	srwi	r3, r3, 31	/* >>31 => select bit 0 */
330	blr
331
332	.globl	dcache_enable
333dcache_enable:
334	lis	r3, 0x0400		/* Set cache mode with MMU off */
335	mtspr	MD_CTR, r3
336
337	lis	r3, IDC_INVALL@h
338	mtspr	DC_CST, r3
339	lis	r3, IDC_ENABLE@h
340	mtspr	DC_CST, r3
341	blr
342
343	.globl	dcache_disable
344dcache_disable:
345	SYNC
346	lis	r3, IDC_DISABLE@h
347	mtspr	DC_CST, r3
348	lis	r3, IDC_INVALL@h
349	mtspr	DC_CST, r3
350	blr
351
352	.globl	dcache_status
353dcache_status:
354	mfspr	r3, DC_CST
355	srwi	r3, r3, 31	/* >>31 => select bit 0 */
356	blr
357
358	.globl	dc_read
359dc_read:
360	mtspr	DC_ADR, r3
361	mfspr	r3, DC_DAT
362	blr
363
364/*
365 * unsigned int get_immr (unsigned int mask)
366 *
367 * return (mask ? (IMMR & mask) : IMMR);
368 */
369	.globl	get_immr
370get_immr:
371	mr	r4,r3		/* save mask */
372	mfspr	r3, IMMR	/* IMMR */
373	cmpwi	0,r4,0		/* mask != 0 ? */
374	beq	4f
375	and	r3,r3,r4	/* IMMR & mask */
3764:
377	blr
378
379	.globl get_pvr
380get_pvr:
381	mfspr	r3, PVR
382	blr
383
384
385	.globl wr_ic_cst
386wr_ic_cst:
387	mtspr	IC_CST, r3
388	blr
389
390	.globl rd_ic_cst
391rd_ic_cst:
392	mfspr	r3, IC_CST
393	blr
394
395	.globl wr_ic_adr
396wr_ic_adr:
397	mtspr	IC_ADR, r3
398	blr
399
400
401	.globl wr_dc_cst
402wr_dc_cst:
403	mtspr	DC_CST, r3
404	blr
405
406	.globl rd_dc_cst
407rd_dc_cst:
408	mfspr	r3, DC_CST
409	blr
410
411	.globl wr_dc_adr
412wr_dc_adr:
413	mtspr	DC_ADR, r3
414	blr
415
416/*------------------------------------------------------------------------------*/
417
418/*
419 * void relocate_code (addr_sp, gd, addr_moni)
420 *
421 * This "function" does not return, instead it continues in RAM
422 * after relocating the monitor code.
423 *
424 * r3 = dest
425 * r4 = src
426 * r5 = length in bytes
427 * r6 = cachelinesize
428 */
429	.globl	relocate_code
430relocate_code:
431	mr	r1,  r3		/* Set new stack pointer		*/
432	mr	r9,  r4		/* Save copy of Global Data pointer	*/
433	mr	r10, r5		/* Save copy of Destination Address	*/
434
435	GET_GOT
436	mr	r3,  r5				/* Destination Address	*/
437	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
438	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
439	lwz	r5, GOT(__init_end)
440	sub	r5, r5, r4
441	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
442
443	/*
444	 * Fix GOT pointer:
445	 *
446	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
447	 *
448	 * Offset:
449	 */
450	sub	r15, r10, r4
451
452	/* First our own GOT */
453	add	r12, r12, r15
454	/* then the one used by the C code */
455	add	r30, r30, r15
456
457	/*
458	 * Now relocate code
459	 */
460
461	cmplw	cr1,r3,r4
462	addi	r0,r5,3
463	srwi.	r0,r0,2
464	beq	cr1,4f		/* In place copy is not necessary	*/
465	beq	7f		/* Protect against 0 count		*/
466	mtctr	r0
467	bge	cr1,2f
468
469	la	r8,-4(r4)
470	la	r7,-4(r3)
4711:	lwzu	r0,4(r8)
472	stwu	r0,4(r7)
473	bdnz	1b
474	b	4f
475
4762:	slwi	r0,r0,2
477	add	r8,r4,r0
478	add	r7,r3,r0
4793:	lwzu	r0,-4(r8)
480	stwu	r0,-4(r7)
481	bdnz	3b
482
483/*
484 * Now flush the cache: note that we must start from a cache aligned
485 * address. Otherwise we might miss one cache line.
486 */
4874:	cmpwi	r6,0
488	add	r5,r3,r5
489	beq	7f		/* Always flush prefetch queue in any case */
490	subi	r0,r6,1
491	andc	r3,r3,r0
492	mr	r4,r3
4935:	dcbst	0,r4
494	add	r4,r4,r6
495	cmplw	r4,r5
496	blt	5b
497	sync			/* Wait for all dcbst to complete on bus */
498	mr	r4,r3
4996:	icbi	0,r4
500	add	r4,r4,r6
501	cmplw	r4,r5
502	blt	6b
5037:	sync			/* Wait for all icbi to complete on bus	*/
504	isync
505
506/*
507 * We are done. Do not return, instead branch to second part of board
508 * initialization, now running from RAM.
509 */
510
511	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
512	mtlr	r0
513	blr
514
515in_ram:
516
517	/*
518	 * Relocation Function, r12 point to got2+0x8000
519	 *
520	 * Adjust got2 pointers, no need to check for 0, this code
521	 * already puts a few entries in the table.
522	 */
523	li	r0,__got2_entries@sectoff@l
524	la	r3,GOT(_GOT2_TABLE_)
525	lwz	r11,GOT(_GOT2_TABLE_)
526	mtctr	r0
527	sub	r11,r3,r11
528	addi	r3,r3,-4
5291:	lwzu	r0,4(r3)
530	cmpwi	r0,0
531	beq-	2f
532	add	r0,r0,r11
533	stw	r0,0(r3)
5342:	bdnz	1b
535
536	/*
537	 * Now adjust the fixups and the pointers to the fixups
538	 * in case we need to move ourselves again.
539	 */
540	li	r0,__fixup_entries@sectoff@l
541	lwz	r3,GOT(_FIXUP_TABLE_)
542	cmpwi	r0,0
543	mtctr	r0
544	addi	r3,r3,-4
545	beq	4f
5463:	lwzu	r4,4(r3)
547	lwzux	r0,r4,r11
548	cmpwi	r0,0
549	add	r0,r0,r11
550	stw	r4,0(r3)
551	beq-	5f
552	stw	r0,0(r4)
5535:	bdnz	3b
5544:
555clear_bss:
556	/*
557	 * Now clear BSS segment
558	 */
559	lwz	r3,GOT(__bss_start)
560	lwz	r4,GOT(__bss_end)
561
562	cmplw	0, r3, r4
563	beq	6f
564
565	li	r0, 0
5665:
567	stw	r0, 0(r3)
568	addi	r3, r3, 4
569	cmplw	0, r3, r4
570	bne	5b
5716:
572
573	mr	r3, r9		/* Global Data pointer		*/
574	mr	r4, r10		/* Destination Address		*/
575	bl	board_init_r
576
577	/*
578	 * Copy exception vector code to low memory
579	 *
580	 * r3: dest_addr
581	 * r7: source address, r8: end address, r9: target address
582	 */
583	.globl	trap_init
584trap_init:
585	mflr	r4			/* save link register		*/
586	GET_GOT
587	lwz	r7, GOT(_start)
588	lwz	r8, GOT(_end_of_vectors)
589
590	li	r9, 0x100		/* reset vector always at 0x100 */
591
592	cmplw	0, r7, r8
593	bgelr				/* return if r7>=r8 - just in case */
5941:
595	lwz	r0, 0(r7)
596	stw	r0, 0(r9)
597	addi	r7, r7, 4
598	addi	r9, r9, 4
599	cmplw	0, r7, r8
600	bne	1b
601
602	/*
603	 * relocate `hdlr' and `int_return' entries
604	 */
605	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
606	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
6072:
608	bl	trap_reloc
609	addi	r7, r7, 0x100		/* next exception vector	*/
610	cmplw	0, r7, r8
611	blt	2b
612
613	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
614	bl	trap_reloc
615
616	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
617	bl	trap_reloc
618
619	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
620	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
6213:
622	bl	trap_reloc
623	addi	r7, r7, 0x100		/* next exception vector	*/
624	cmplw	0, r7, r8
625	blt	3b
626
627	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
628	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6294:
630	bl	trap_reloc
631	addi	r7, r7, 0x100		/* next exception vector	*/
632	cmplw	0, r7, r8
633	blt	4b
634
635	mtlr	r4			/* restore link register	*/
636	blr
637