1 /*
2  * (C) Copyright 2000-2002
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <mpc8xx.h>
10 #include <mpc8xx_irq.h>
11 #include <asm/processor.h>
12 #include <asm/io.h>
13 #include <commproc.h>
14 
15 /************************************************************************/
16 
17 /*
18  * CPM interrupt vector functions.
19  */
20 struct interrupt_action {
21 	interrupt_handler_t *handler;
22 	void *arg;
23 };
24 
25 static struct interrupt_action cpm_vecs[CPMVEC_NR];
26 static struct interrupt_action irq_vecs[NR_IRQS];
27 
28 static void cpm_interrupt_init(void);
29 static void cpm_interrupt(void *regs);
30 
31 /************************************************************************/
32 
33 int interrupt_init_cpu(unsigned *decrementer_count)
34 {
35 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
36 
37 	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
38 
39 	/* disable all interrupts */
40 	out_be32(&immr->im_siu_conf.sc_simask, 0);
41 
42 	/* Configure CPM interrupts */
43 	cpm_interrupt_init();
44 
45 	return 0;
46 }
47 
48 /************************************************************************/
49 
50 /*
51  * Handle external interrupts
52  */
53 void external_interrupt(struct pt_regs *regs)
54 {
55 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
56 	int irq;
57 	ulong simask;
58 	ulong vec, v_bit;
59 
60 	/*
61 	 * read the SIVEC register and shift the bits down
62 	 * to get the irq number
63 	 */
64 	vec = in_be32(&immr->im_siu_conf.sc_sivec);
65 	irq = vec >> 26;
66 	v_bit = 0x80000000UL >> irq;
67 
68 	/*
69 	 * Read Interrupt Mask Register and Mask Interrupts
70 	 */
71 	simask = in_be32(&immr->im_siu_conf.sc_simask);
72 	clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
73 
74 	if (!(irq & 0x1)) {		/* External Interrupt ?     */
75 		ulong siel;
76 
77 		/*
78 		 * Read Interrupt Edge/Level Register
79 		 */
80 		siel = in_be32(&immr->im_siu_conf.sc_siel);
81 
82 		if (siel & v_bit) {	/* edge triggered interrupt ?   */
83 			/*
84 			 * Rewrite SIPEND Register to clear interrupt
85 			 */
86 			out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
87 		}
88 	}
89 
90 	if (irq_vecs[irq].handler != NULL) {
91 		irq_vecs[irq].handler(irq_vecs[irq].arg);
92 	} else {
93 		printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
94 		       irq, vec);
95 		/* turn off the bogus interrupt to avoid it from now */
96 		simask &= ~v_bit;
97 	}
98 	/*
99 	 * Re-Enable old Interrupt Mask
100 	 */
101 	out_be32(&immr->im_siu_conf.sc_simask, simask);
102 }
103 
104 /************************************************************************/
105 
106 /*
107  * CPM interrupt handler
108  */
109 static void cpm_interrupt(void *regs)
110 {
111 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
112 	uint vec;
113 
114 	/*
115 	 * Get the vector by setting the ACK bit
116 	 * and then reading the register.
117 	 */
118 	out_be16(&immr->im_cpic.cpic_civr, 1);
119 	vec = in_be16(&immr->im_cpic.cpic_civr);
120 	vec >>= 11;
121 
122 	if (cpm_vecs[vec].handler != NULL) {
123 		(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
124 	} else {
125 		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
126 		printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
127 	}
128 	/*
129 	 * After servicing the interrupt,
130 	 * we have to remove the status indicator.
131 	 */
132 	setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
133 }
134 
135 /*
136  * The CPM can generate the error interrupt when there is a race
137  * condition between generating and masking interrupts. All we have
138  * to do is ACK it and return. This is a no-op function so we don't
139  * need any special tests in the interrupt handler.
140  */
141 static void cpm_error_interrupt(void *dummy)
142 {
143 }
144 
145 /************************************************************************/
146 /*
147  * Install and free an interrupt handler
148  */
149 void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
150 {
151 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
152 
153 	if ((vec & CPMVEC_OFFSET) != 0) {
154 		/* CPM interrupt */
155 		vec &= 0xffff;
156 		if (cpm_vecs[vec].handler != NULL)
157 			printf("CPM interrupt 0x%x replacing 0x%x\n",
158 			       (uint)handler, (uint)cpm_vecs[vec].handler);
159 		cpm_vecs[vec].handler = handler;
160 		cpm_vecs[vec].arg = arg;
161 		setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
162 	} else {
163 		/* SIU interrupt */
164 		if (irq_vecs[vec].handler != NULL)
165 			printf("SIU interrupt %d 0x%x replacing 0x%x\n",
166 			       vec, (uint)handler, (uint)cpm_vecs[vec].handler);
167 		irq_vecs[vec].handler = handler;
168 		irq_vecs[vec].arg = arg;
169 		setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
170 	}
171 }
172 
173 void irq_free_handler(int vec)
174 {
175 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
176 
177 	if ((vec & CPMVEC_OFFSET) != 0) {
178 		/* CPM interrupt */
179 		vec &= 0xffff;
180 		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
181 		cpm_vecs[vec].handler = NULL;
182 		cpm_vecs[vec].arg = NULL;
183 	} else {
184 		/* SIU interrupt */
185 		clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
186 		irq_vecs[vec].handler = NULL;
187 		irq_vecs[vec].arg = NULL;
188 	}
189 }
190 
191 /************************************************************************/
192 
193 static void cpm_interrupt_init(void)
194 {
195 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
196 	uint cicr;
197 
198 	/*
199 	 * Initialize the CPM interrupt controller.
200 	 */
201 
202 	cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
203 	       ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
204 
205 	out_be32(&immr->im_cpic.cpic_cicr, cicr);
206 	out_be32(&immr->im_cpic.cpic_cimr, 0);
207 
208 	/*
209 	 * Install the error handler.
210 	 */
211 	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
212 
213 	setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
214 
215 	/*
216 	 * Install the cpm interrupt handler
217 	 */
218 	irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
219 }
220 
221 /************************************************************************/
222 
223 /*
224  * timer_interrupt - gets called when the decrementer overflows,
225  * with interrupts disabled.
226  * Trivial implementation - no need to be really accurate.
227  */
228 void timer_interrupt_cpu(struct pt_regs *regs)
229 {
230 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
231 
232 	/* Reset Timer Expired and Timers Interrupt Status */
233 	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
234 	__asm__ ("nop");
235 	/*
236 	  Clear TEXPS (and TMIST on older chips). SPLSS (on older
237 	  chips) is cleared too.
238 
239 	  Bitwise OR is a read-modify-write operation so ALL bits
240 	  which are cleared by writing `1' would be cleared by
241 	  operations like
242 
243 	  immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
244 
245 	  The same can be achieved by simple writing of the PLPRCR
246 	  to itself. If a bit value should be preserved, read the
247 	  register, ZERO the bit and write, not OR, the result back.
248 	*/
249 	setbits_be32(&immr->im_clkrst.car_plprcr, 0);
250 }
251 
252 /************************************************************************/
253