1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mpc8xx.h> 10 #include <mpc8xx_irq.h> 11 #include <asm/processor.h> 12 #include <commproc.h> 13 14 /************************************************************************/ 15 16 /* 17 * CPM interrupt vector functions. 18 */ 19 struct interrupt_action { 20 interrupt_handler_t *handler; 21 void *arg; 22 }; 23 24 static struct interrupt_action cpm_vecs[CPMVEC_NR]; 25 static struct interrupt_action irq_vecs[NR_IRQS]; 26 27 static void cpm_interrupt_init (void); 28 static void cpm_interrupt (void *regs); 29 30 /************************************************************************/ 31 32 int interrupt_init_cpu (unsigned *decrementer_count) 33 { 34 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 35 36 *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; 37 38 /* disable all interrupts */ 39 immr->im_siu_conf.sc_simask = 0; 40 41 /* Configure CPM interrupts */ 42 cpm_interrupt_init (); 43 44 return (0); 45 } 46 47 /************************************************************************/ 48 49 /* 50 * Handle external interrupts 51 */ 52 void external_interrupt (struct pt_regs *regs) 53 { 54 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 55 int irq; 56 ulong simask, newmask; 57 ulong vec, v_bit; 58 59 /* 60 * read the SIVEC register and shift the bits down 61 * to get the irq number 62 */ 63 vec = immr->im_siu_conf.sc_sivec; 64 irq = vec >> 26; 65 v_bit = 0x80000000UL >> irq; 66 67 /* 68 * Read Interrupt Mask Register and Mask Interrupts 69 */ 70 simask = immr->im_siu_conf.sc_simask; 71 newmask = simask & (~(0xFFFF0000 >> irq)); 72 immr->im_siu_conf.sc_simask = newmask; 73 74 if (!(irq & 0x1)) { /* External Interrupt ? */ 75 ulong siel; 76 77 /* 78 * Read Interrupt Edge/Level Register 79 */ 80 siel = immr->im_siu_conf.sc_siel; 81 82 if (siel & v_bit) { /* edge triggered interrupt ? */ 83 /* 84 * Rewrite SIPEND Register to clear interrupt 85 */ 86 immr->im_siu_conf.sc_sipend = v_bit; 87 } 88 } 89 90 if (irq_vecs[irq].handler != NULL) { 91 irq_vecs[irq].handler (irq_vecs[irq].arg); 92 } else { 93 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", 94 irq, vec); 95 /* turn off the bogus interrupt to avoid it from now */ 96 simask &= ~v_bit; 97 } 98 /* 99 * Re-Enable old Interrupt Mask 100 */ 101 immr->im_siu_conf.sc_simask = simask; 102 } 103 104 /************************************************************************/ 105 106 /* 107 * CPM interrupt handler 108 */ 109 static void cpm_interrupt (void *regs) 110 { 111 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 112 uint vec; 113 114 /* 115 * Get the vector by setting the ACK bit 116 * and then reading the register. 117 */ 118 immr->im_cpic.cpic_civr = 1; 119 vec = immr->im_cpic.cpic_civr; 120 vec >>= 11; 121 122 if (cpm_vecs[vec].handler != NULL) { 123 (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); 124 } else { 125 immr->im_cpic.cpic_cimr &= ~(1 << vec); 126 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); 127 } 128 /* 129 * After servicing the interrupt, 130 * we have to remove the status indicator. 131 */ 132 immr->im_cpic.cpic_cisr |= (1 << vec); 133 } 134 135 /* 136 * The CPM can generate the error interrupt when there is a race 137 * condition between generating and masking interrupts. All we have 138 * to do is ACK it and return. This is a no-op function so we don't 139 * need any special tests in the interrupt handler. 140 */ 141 static void cpm_error_interrupt (void *dummy) 142 { 143 } 144 145 /************************************************************************/ 146 /* 147 * Install and free an interrupt handler 148 */ 149 void irq_install_handler (int vec, interrupt_handler_t * handler, 150 void *arg) 151 { 152 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 153 154 if ((vec & CPMVEC_OFFSET) != 0) { 155 /* CPM interrupt */ 156 vec &= 0xffff; 157 if (cpm_vecs[vec].handler != NULL) { 158 printf ("CPM interrupt 0x%x replacing 0x%x\n", 159 (uint) handler, 160 (uint) cpm_vecs[vec].handler); 161 } 162 cpm_vecs[vec].handler = handler; 163 cpm_vecs[vec].arg = arg; 164 immr->im_cpic.cpic_cimr |= (1 << vec); 165 #if 0 166 printf ("Install CPM interrupt for vector %d ==> %p\n", 167 vec, handler); 168 #endif 169 } else { 170 /* SIU interrupt */ 171 if (irq_vecs[vec].handler != NULL) { 172 printf ("SIU interrupt %d 0x%x replacing 0x%x\n", 173 vec, 174 (uint) handler, 175 (uint) cpm_vecs[vec].handler); 176 } 177 irq_vecs[vec].handler = handler; 178 irq_vecs[vec].arg = arg; 179 immr->im_siu_conf.sc_simask |= 1 << (31 - vec); 180 #if 0 181 printf ("Install SIU interrupt for vector %d ==> %p\n", 182 vec, handler); 183 #endif 184 } 185 } 186 187 void irq_free_handler (int vec) 188 { 189 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 190 191 if ((vec & CPMVEC_OFFSET) != 0) { 192 /* CPM interrupt */ 193 vec &= 0xffff; 194 #if 0 195 printf ("Free CPM interrupt for vector %d ==> %p\n", 196 vec, cpm_vecs[vec].handler); 197 #endif 198 immr->im_cpic.cpic_cimr &= ~(1 << vec); 199 cpm_vecs[vec].handler = NULL; 200 cpm_vecs[vec].arg = NULL; 201 } else { 202 /* SIU interrupt */ 203 #if 0 204 printf ("Free CPM interrupt for vector %d ==> %p\n", 205 vec, cpm_vecs[vec].handler); 206 #endif 207 immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); 208 irq_vecs[vec].handler = NULL; 209 irq_vecs[vec].arg = NULL; 210 } 211 } 212 213 /************************************************************************/ 214 215 static void cpm_interrupt_init (void) 216 { 217 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 218 219 /* 220 * Initialize the CPM interrupt controller. 221 */ 222 223 immr->im_cpic.cpic_cicr = 224 (CICR_SCD_SCC4 | 225 CICR_SCC_SCC3 | 226 CICR_SCB_SCC2 | 227 CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; 228 229 immr->im_cpic.cpic_cimr = 0; 230 231 /* 232 * Install the error handler. 233 */ 234 irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); 235 236 immr->im_cpic.cpic_cicr |= CICR_IEN; 237 238 /* 239 * Install the cpm interrupt handler 240 */ 241 irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); 242 } 243 244 /************************************************************************/ 245 246 /* 247 * timer_interrupt - gets called when the decrementer overflows, 248 * with interrupts disabled. 249 * Trivial implementation - no need to be really accurate. 250 */ 251 void timer_interrupt_cpu (struct pt_regs *regs) 252 { 253 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 254 255 #if 0 256 printf ("*** Timer Interrupt *** "); 257 #endif 258 /* Reset Timer Expired and Timers Interrupt Status */ 259 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; 260 __asm__ ("nop"); 261 /* 262 Clear TEXPS (and TMIST on older chips). SPLSS (on older 263 chips) is cleared too. 264 265 Bitwise OR is a read-modify-write operation so ALL bits 266 which are cleared by writing `1' would be cleared by 267 operations like 268 269 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; 270 271 The same can be achieved by simple writing of the PLPRCR 272 to itself. If a bit value should be preserved, read the 273 register, ZERO the bit and write, not OR, the result back. 274 */ 275 immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; 276 } 277 278 /************************************************************************/ 279