1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2000-2002
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  */
6 
7 #include <common.h>
8 #include <watchdog.h>
9 
10 #include <mpc8xx.h>
11 #include <asm/cpm_8xx.h>
12 #include <asm/io.h>
13 
14 /*
15  * Breath some life into the CPU...
16  *
17  * Set up the memory map,
18  * initialize a bunch of registers,
19  * initialize the UPM's
20  */
21 void cpu_init_f(immap_t __iomem *immr)
22 {
23 	memctl8xx_t __iomem *memctl = &immr->im_memctl;
24 	ulong reg;
25 
26 	/* SYPCR - contains watchdog control (11-9) */
27 
28 #ifndef CONFIG_HW_WATCHDOG
29 	/* deactivate watchdog if not enabled in config */
30 	out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
31 #endif
32 
33 	WATCHDOG_RESET();
34 
35 	/* SIUMCR - contains debug pin configuration (11-6) */
36 	setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
37 	/* initialize timebase status and control register (11-26) */
38 	/* unlock TBSCRK */
39 
40 	out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
41 	out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
42 
43 	/* Unlock timebase register */
44 	out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
45 
46 	/* initialize the PIT (11-31) */
47 
48 	out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
49 	out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
50 
51 	/* System integration timers. Don't change EBDF! (15-27) */
52 
53 	out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
54 	clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
55 			CONFIG_SYS_SCCR);
56 
57 	/*
58 	 * MPC866/885 ERRATA GLL2
59 	 * Description:
60 	 *   In 1:2:1 mode, when HRESET is detected at the positive edge of
61 	 *   EXTCLK, then there will be a loss of phase between
62 	 *   EXTCLK and CLKOUT.
63 	 *
64 	 * Workaround:
65 	 *   Reprogram the SCCR:
66 	 *   1.   Write 1'b00 to SCCR[EBDF].
67 	 *   2.   Write 1'b01 to SCCR[EBDF].
68 	 *   3.   Rewrite the desired value to the PLPRCR register.
69 	 */
70 	reg = in_be32(&immr->im_clkrst.car_sccr);
71 	/* Are we in mode 1:2:1 ? */
72 	if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
73 		clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
74 		setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
75 	}
76 
77 	/* PLL (CPU clock) settings (15-30) */
78 
79 	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
80 
81 	/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
82 	 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
83 	 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
84 	 * field value.
85 	 *
86 	 * For newer (starting MPC866) chips PLPRCR layout is different.
87 	 */
88 #ifdef CONFIG_SYS_PLPRCR
89 	if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
90 		out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
91 	else /* isolate MF-related fields and reset control bits */
92 		clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
93 				CONFIG_SYS_PLPRCR);
94 #endif
95 
96 	/*
97 	 * Memory Controller:
98 	 */
99 
100 	/* Clear everything except Port Size bits & add the "Bank Valid" bit */
101 	clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
102 
103 	/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
104 	 * preliminary addresses - these have to be modified later
105 	 * when FLASH size has been determined
106 	 *
107 	 * Depending on the size of the memory region defined by
108 	 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
109 	 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
110 	 * map CONFIG_SYS_MONITOR_BASE.
111 	 *
112 	 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
113 	 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
114 	 *
115 	 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
116 	 * base address remains as 0x00000000. However, the address mask
117 	 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
118 	 * into the Bank0.
119 	 *
120 	 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
121 	 * CONFIG_SYS_BR0_PRELIM in advance.
122 	 *
123 	 * [Thanks to Michael Liao for this explanation.
124 	 *  I owe him a free beer. - wd]
125 	 */
126 
127 #if defined(CONFIG_SYS_OR0_REMAP)
128 	out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
129 #endif
130 #if defined(CONFIG_SYS_OR1_REMAP)
131 	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
132 #endif
133 #if defined(CONFIG_SYS_OR5_REMAP)
134 	out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
135 #endif
136 
137 	/* now restrict to preliminary range */
138 	out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
139 	out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
140 
141 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
142 	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
143 	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
144 #endif
145 
146 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
147 	out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
148 	out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
149 #endif
150 
151 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
152 	out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
153 	out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
154 #endif
155 
156 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
157 	out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
158 	out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
159 #endif
160 
161 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
162 	out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
163 	out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
164 #endif
165 
166 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
167 	out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
168 	out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
169 #endif
170 
171 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
172 	out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
173 	out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
174 #endif
175 
176 	/*
177 	 * Reset CPM
178 	 */
179 	out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
180 	/* Spin until command processed */
181 	while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
182 		;
183 }
184 
185 /*
186  * initialize higher level parts of CPU like timers
187  */
188 int cpu_init_r(void)
189 {
190 	return 0;
191 }
192