1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * m8xx.c 26 * 27 * CPU specific code 28 * 29 * written or collected and sometimes rewritten by 30 * Magnus Damm <damm@bitsmart.com> 31 * 32 * minor modifications by 33 * Wolfgang Denk <wd@denx.de> 34 */ 35 36 #include <common.h> 37 #include <watchdog.h> 38 #include <command.h> 39 #include <mpc8xx.h> 40 #include <commproc.h> 41 #include <netdev.h> 42 #include <asm/cache.h> 43 44 #if defined(CONFIG_OF_LIBFDT) 45 #include <libfdt.h> 46 #include <libfdt_env.h> 47 #include <fdt_support.h> 48 #endif 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 static char *cpu_warning = "\n " \ 53 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; 54 55 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ 56 !defined(CONFIG_MPC862)) 57 58 static int check_CPU (long clock, uint pvr, uint immr) 59 { 60 char *id_str = 61 # if defined(CONFIG_MPC855) 62 "PC855"; 63 # elif defined(CONFIG_MPC860P) 64 "PC860P"; 65 # else 66 NULL; 67 # endif 68 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 69 uint k, m; 70 char buf[32]; 71 char pre = 'X'; 72 char *mid = "xx"; 73 char *suf; 74 75 /* the highest 16 bits should be 0x0050 for a 860 */ 76 77 if ((pvr >> 16) != 0x0050) 78 return -1; 79 80 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 81 m = 0; 82 suf = ""; 83 84 /* 85 * Some boards use sockets so different CPUs can be used. 86 * We have to check chip version in run time. 87 */ 88 switch (k) { 89 case 0x00020001: pre = 'P'; break; 90 case 0x00030001: break; 91 case 0x00120003: suf = "A"; break; 92 case 0x00130003: suf = "A3"; break; 93 94 case 0x00200004: suf = "B"; break; 95 96 case 0x00300004: suf = "C"; break; 97 case 0x00310004: suf = "C1"; m = 1; break; 98 99 case 0x00200064: mid = "SR"; suf = "B"; break; 100 case 0x00300065: mid = "SR"; suf = "C"; break; 101 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; 102 case 0x05010000: suf = "D3"; m = 1; break; 103 case 0x05020000: suf = "D4"; m = 1; break; 104 /* this value is not documented anywhere */ 105 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; 106 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ 107 case 0x08010004: /* Rev. A.0 */ 108 suf = "A"; 109 /* fall through */ 110 case 0x08000003: /* Rev. 0.3 */ 111 pre = 'M'; m = 1; 112 if (id_str == NULL) 113 id_str = 114 # if defined(CONFIG_MPC852T) 115 "PC852T"; 116 # elif defined(CONFIG_MPC859T) 117 "PC859T"; 118 # elif defined(CONFIG_MPC859DSL) 119 "PC859DSL"; 120 # elif defined(CONFIG_MPC866T) 121 "PC866T"; 122 # else 123 "PC866x"; /* Unknown chip from MPC866 family */ 124 # endif 125 break; 126 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; 127 if (id_str == NULL) 128 id_str = "PC885"; /* 870/875/880/885 */ 129 break; 130 131 default: suf = NULL; break; 132 } 133 134 if (id_str == NULL) 135 id_str = "PC86x"; /* Unknown 86x chip */ 136 if (suf) 137 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); 138 else 139 printf ("unknown M%s (0x%08x)", id_str, k); 140 141 142 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) 143 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", 144 strmhz (buf, clock), 145 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, 146 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, 147 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, 148 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 149 ); 150 #else 151 printf (" at %s MHz: ", strmhz (buf, clock)); 152 #endif 153 printf ("%u kB I-Cache %u kB D-Cache", 154 checkicache () >> 10, 155 checkdcache () >> 10 156 ); 157 158 /* do we have a FEC (860T/P or 852/859/866/885)? */ 159 160 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 161 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 162 printf (" FEC present"); 163 } 164 165 if (!m) { 166 puts (cpu_warning); 167 } 168 169 putc ('\n'); 170 171 #ifdef DEBUG 172 if(clock != measure_gclk()) { 173 printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); 174 } 175 #endif 176 177 return 0; 178 } 179 180 #elif defined(CONFIG_MPC862) 181 182 static int check_CPU (long clock, uint pvr, uint immr) 183 { 184 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 185 uint k, m; 186 char buf[32]; 187 char pre = 'X'; 188 char *mid = "xx"; 189 char *suf; 190 191 /* the highest 16 bits should be 0x0050 for a 8xx */ 192 193 if ((pvr >> 16) != 0x0050) 194 return -1; 195 196 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 197 m = 0; 198 199 switch (k) { 200 201 /* this value is not documented anywhere */ 202 case 0x06000000: mid = "P"; suf = "0"; break; 203 case 0x06010001: mid = "P"; suf = "A"; m = 1; break; 204 case 0x07000003: mid = "P"; suf = "B"; m = 1; break; 205 default: suf = NULL; break; 206 } 207 208 #ifndef CONFIG_MPC857 209 if (suf) 210 printf ("%cPC862%sZPnn%s", pre, mid, suf); 211 else 212 printf ("unknown MPC862 (0x%08x)", k); 213 #else 214 if (suf) 215 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ 216 else 217 printf ("unknown MPC857 (0x%08x)", k); 218 #endif 219 220 printf (" at %s MHz:", strmhz (buf, clock)); 221 222 printf (" %u kB I-Cache", checkicache () >> 10); 223 printf (" %u kB D-Cache", checkdcache () >> 10); 224 225 /* lets check and see if we're running on a 862T (or P?) */ 226 227 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 228 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 229 printf (" FEC present"); 230 } 231 232 if (!m) { 233 puts (cpu_warning); 234 } 235 236 putc ('\n'); 237 238 return 0; 239 } 240 241 #elif defined(CONFIG_MPC823) 242 243 static int check_CPU (long clock, uint pvr, uint immr) 244 { 245 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 246 uint k, m; 247 char buf[32]; 248 char *suf; 249 250 /* the highest 16 bits should be 0x0050 for a 8xx */ 251 252 if ((pvr >> 16) != 0x0050) 253 return -1; 254 255 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 256 m = 0; 257 258 switch (k) { 259 /* MPC823 */ 260 case 0x20000000: suf = "0"; break; 261 case 0x20010000: suf = "0.1"; break; 262 case 0x20020000: suf = "Z2/3"; break; 263 case 0x20020001: suf = "Z3"; break; 264 case 0x21000000: suf = "A"; break; 265 case 0x21010000: suf = "B"; m = 1; break; 266 case 0x21010001: suf = "B2"; m = 1; break; 267 /* MPC823E */ 268 case 0x24010000: suf = NULL; 269 puts ("PPC823EZTnnB2"); 270 m = 1; 271 break; 272 default: 273 suf = NULL; 274 printf ("unknown MPC823 (0x%08x)", k); 275 break; 276 } 277 if (suf) 278 printf ("PPC823ZTnn%s", suf); 279 280 printf (" at %s MHz:", strmhz (buf, clock)); 281 282 printf (" %u kB I-Cache", checkicache () >> 10); 283 printf (" %u kB D-Cache", checkdcache () >> 10); 284 285 /* lets check and see if we're running on a 860T (or P?) */ 286 287 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 288 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 289 puts (" FEC present"); 290 } 291 292 if (!m) { 293 puts (cpu_warning); 294 } 295 296 putc ('\n'); 297 298 return 0; 299 } 300 301 #elif defined(CONFIG_MPC850) 302 303 static int check_CPU (long clock, uint pvr, uint immr) 304 { 305 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 306 uint k, m; 307 char buf[32]; 308 309 /* the highest 16 bits should be 0x0050 for a 8xx */ 310 311 if ((pvr >> 16) != 0x0050) 312 return -1; 313 314 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 315 m = 0; 316 317 switch (k) { 318 case 0x20020001: 319 printf ("XPC850xxZT"); 320 break; 321 case 0x21000065: 322 printf ("XPC850xxZTA"); 323 break; 324 case 0x21010067: 325 printf ("XPC850xxZTB"); 326 m = 1; 327 break; 328 case 0x21020068: 329 printf ("XPC850xxZTC"); 330 m = 1; 331 break; 332 default: 333 printf ("unknown MPC850 (0x%08x)", k); 334 } 335 printf (" at %s MHz:", strmhz (buf, clock)); 336 337 printf (" %u kB I-Cache", checkicache () >> 10); 338 printf (" %u kB D-Cache", checkdcache () >> 10); 339 340 /* lets check and see if we're running on a 850T (or P?) */ 341 342 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 343 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 344 printf (" FEC present"); 345 } 346 347 if (!m) { 348 puts (cpu_warning); 349 } 350 351 putc ('\n'); 352 353 return 0; 354 } 355 #else 356 #error CPU undefined 357 #endif 358 /* ------------------------------------------------------------------------- */ 359 360 int checkcpu (void) 361 { 362 ulong clock = gd->cpu_clk; 363 uint immr = get_immr (0); /* Return full IMMR contents */ 364 uint pvr = get_pvr (); 365 366 puts ("CPU: "); 367 368 /* 850 has PARTNUM 20 */ 369 /* 801 has PARTNUM 10 */ 370 return check_CPU (clock, pvr, immr); 371 } 372 373 /* ------------------------------------------------------------------------- */ 374 /* L1 i-cache */ 375 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 376 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ 377 378 int checkicache (void) 379 { 380 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 381 volatile memctl8xx_t *memctl = &immap->im_memctl; 382 u32 cacheon = rd_ic_cst () & IDC_ENABLED; 383 384 #ifdef CONFIG_IP86x 385 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 386 #else 387 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 388 #endif 389 u32 m; 390 u32 lines = -1; 391 392 wr_ic_cst (IDC_UNALL); 393 wr_ic_cst (IDC_INVALL); 394 wr_ic_cst (IDC_DISABLE); 395 __asm__ volatile ("isync"); 396 397 while (!((m = rd_ic_cst ()) & IDC_CERR2)) { 398 wr_ic_adr (k); 399 wr_ic_cst (IDC_LDLCK); 400 __asm__ volatile ("isync"); 401 402 lines++; 403 k += 0x10; /* the number of bytes in a cacheline */ 404 } 405 406 wr_ic_cst (IDC_UNALL); 407 wr_ic_cst (IDC_INVALL); 408 409 if (cacheon) 410 wr_ic_cst (IDC_ENABLE); 411 else 412 wr_ic_cst (IDC_DISABLE); 413 414 __asm__ volatile ("isync"); 415 416 return lines << 4; 417 }; 418 419 /* ------------------------------------------------------------------------- */ 420 /* L1 d-cache */ 421 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 422 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ 423 /* call with cache disabled */ 424 425 int checkdcache (void) 426 { 427 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 428 volatile memctl8xx_t *memctl = &immap->im_memctl; 429 u32 cacheon = rd_dc_cst () & IDC_ENABLED; 430 431 #ifdef CONFIG_IP86x 432 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 433 #else 434 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 435 #endif 436 u32 m; 437 u32 lines = -1; 438 439 wr_dc_cst (IDC_UNALL); 440 wr_dc_cst (IDC_INVALL); 441 wr_dc_cst (IDC_DISABLE); 442 443 while (!((m = rd_dc_cst ()) & IDC_CERR2)) { 444 wr_dc_adr (k); 445 wr_dc_cst (IDC_LDLCK); 446 lines++; 447 k += 0x10; /* the number of bytes in a cacheline */ 448 } 449 450 wr_dc_cst (IDC_UNALL); 451 wr_dc_cst (IDC_INVALL); 452 453 if (cacheon) 454 wr_dc_cst (IDC_ENABLE); 455 else 456 wr_dc_cst (IDC_DISABLE); 457 458 return lines << 4; 459 }; 460 461 /* ------------------------------------------------------------------------- */ 462 463 void upmconfig (uint upm, uint * table, uint size) 464 { 465 uint i; 466 uint addr = 0; 467 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 468 volatile memctl8xx_t *memctl = &immap->im_memctl; 469 470 for (i = 0; i < size; i++) { 471 memctl->memc_mdr = table[i]; /* (16-15) */ 472 memctl->memc_mcr = addr | upm; /* (16-16) */ 473 addr++; 474 } 475 } 476 477 /* ------------------------------------------------------------------------- */ 478 479 #ifndef CONFIG_LWMON 480 481 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 482 { 483 ulong msr, addr; 484 485 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 486 487 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ 488 489 /* Interrupts and MMU off */ 490 __asm__ volatile ("mtspr 81, 0"); 491 __asm__ volatile ("mfmsr %0":"=r" (msr)); 492 493 msr &= ~0x1030; 494 __asm__ volatile ("mtmsr %0"::"r" (msr)); 495 496 /* 497 * Trying to execute the next instruction at a non-existing address 498 * should cause a machine check, resulting in reset 499 */ 500 #ifdef CONFIG_SYS_RESET_ADDRESS 501 addr = CONFIG_SYS_RESET_ADDRESS; 502 #else 503 /* 504 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE 505 * - sizeof (ulong) is usually a valid address. Better pick an address 506 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. 507 * "(ulong)-1" used to be a good choice for many systems... 508 */ 509 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); 510 #endif 511 ((void (*)(void)) addr) (); 512 return 1; 513 } 514 515 #else /* CONFIG_LWMON */ 516 517 /* 518 * On the LWMON board, the MCLR reset input of the PIC's on the board 519 * uses a 47K/1n RC combination which has a 47us time constant. The 520 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us 521 * and thus too short to reset the external hardware. So we use the 522 * watchdog to reset the board. 523 */ 524 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 525 { 526 /* prevent triggering the watchdog */ 527 disable_interrupts (); 528 529 /* make sure the watchdog is running */ 530 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 531 532 /* wait for watchdog reset */ 533 while (1) {}; 534 535 /* NOTREACHED */ 536 return 1; 537 } 538 539 #endif /* CONFIG_LWMON */ 540 541 /* ------------------------------------------------------------------------- */ 542 543 /* 544 * Get timebase clock frequency (like cpu_clk in Hz) 545 * 546 * See sections 14.2 and 14.6 of the User's Manual 547 */ 548 unsigned long get_tbclk (void) 549 { 550 uint immr = get_immr (0); /* Return full IMMR contents */ 551 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); 552 ulong oscclk, factor, pll; 553 554 if (immap->im_clkrst.car_sccr & SCCR_TBS) { 555 return (gd->cpu_clk / 16); 556 } 557 558 pll = immap->im_clkrst.car_plprcr; 559 560 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) 561 562 /* 563 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication 564 * factor is calculated as follows: 565 * 566 * MFN 567 * MFI + ------- 568 * MFD + 1 569 * factor = ----------------- 570 * (PDF + 1) * 2^S 571 * 572 * For older chips, it's just MF field of PLPRCR plus one. 573 */ 574 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ 575 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ 576 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); 577 } else { 578 factor = PLPRCR_val(MF)+1; 579 } 580 581 oscclk = gd->cpu_clk / factor; 582 583 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { 584 return (oscclk / 4); 585 } 586 return (oscclk / 16); 587 } 588 589 /* ------------------------------------------------------------------------- */ 590 591 #if defined(CONFIG_WATCHDOG) 592 void watchdog_reset (void) 593 { 594 int re_enable = disable_interrupts (); 595 596 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 597 if (re_enable) 598 enable_interrupts (); 599 } 600 #endif /* CONFIG_WATCHDOG */ 601 602 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) 603 604 void reset_8xx_watchdog (volatile immap_t * immr) 605 { 606 # if defined(CONFIG_LWMON) 607 /* 608 * The LWMON board uses a MAX6301 Watchdog 609 * with the trigger pin connected to port PA.7 610 * 611 * (The old board version used a MAX706TESA Watchdog, which 612 * had to be handled exactly the same.) 613 */ 614 # define WATCHDOG_BIT 0x0100 615 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 616 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 617 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 618 619 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 620 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 621 /* 622 * The KUP4 boards uses a TPS3705 Watchdog 623 * with the trigger pin connected to port PA.5 624 */ 625 # define WATCHDOG_BIT 0x0400 626 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 627 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 628 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 629 630 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 631 # else 632 /* 633 * All other boards use the MPC8xx Internal Watchdog 634 */ 635 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ 636 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ 637 # endif /* CONFIG_LWMON */ 638 } 639 #endif /* CONFIG_WATCHDOG */ 640 641 /* 642 * Initializes on-chip ethernet controllers. 643 * to override, implement board_eth_init() 644 */ 645 int cpu_eth_init(bd_t *bis) 646 { 647 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET) 648 scc_initialize(bis); 649 #endif 650 #if defined(FEC_ENET) 651 fec_initialize(bis); 652 #endif 653 return 0; 654 } 655