1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * m8xx.c 26 * 27 * CPU specific code 28 * 29 * written or collected and sometimes rewritten by 30 * Magnus Damm <damm@bitsmart.com> 31 * 32 * minor modifications by 33 * Wolfgang Denk <wd@denx.de> 34 */ 35 36 #include <common.h> 37 #include <watchdog.h> 38 #include <command.h> 39 #include <mpc8xx.h> 40 #include <commproc.h> 41 #include <netdev.h> 42 #include <asm/cache.h> 43 #include <linux/compiler.h> 44 #include <asm/io.h> 45 46 #if defined(CONFIG_OF_LIBFDT) 47 #include <libfdt.h> 48 #include <libfdt_env.h> 49 #include <fdt_support.h> 50 #endif 51 52 DECLARE_GLOBAL_DATA_PTR; 53 54 static char *cpu_warning = "\n " \ 55 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; 56 57 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ 58 !defined(CONFIG_MPC862)) 59 60 static int check_CPU (long clock, uint pvr, uint immr) 61 { 62 char *id_str = 63 # if defined(CONFIG_MPC855) 64 "PC855"; 65 # elif defined(CONFIG_MPC860P) 66 "PC860P"; 67 # else 68 NULL; 69 # endif 70 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 71 uint k, m; 72 char buf[32]; 73 char pre = 'X'; 74 char *mid = "xx"; 75 char *suf; 76 77 /* the highest 16 bits should be 0x0050 for a 860 */ 78 79 if ((pvr >> 16) != 0x0050) 80 return -1; 81 82 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 83 m = 0; 84 suf = ""; 85 86 /* 87 * Some boards use sockets so different CPUs can be used. 88 * We have to check chip version in run time. 89 */ 90 switch (k) { 91 case 0x00020001: pre = 'P'; break; 92 case 0x00030001: break; 93 case 0x00120003: suf = "A"; break; 94 case 0x00130003: suf = "A3"; break; 95 96 case 0x00200004: suf = "B"; break; 97 98 case 0x00300004: suf = "C"; break; 99 case 0x00310004: suf = "C1"; m = 1; break; 100 101 case 0x00200064: mid = "SR"; suf = "B"; break; 102 case 0x00300065: mid = "SR"; suf = "C"; break; 103 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; 104 case 0x05010000: suf = "D3"; m = 1; break; 105 case 0x05020000: suf = "D4"; m = 1; break; 106 /* this value is not documented anywhere */ 107 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; 108 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ 109 case 0x08010004: /* Rev. A.0 */ 110 suf = "A"; 111 /* fall through */ 112 case 0x08000003: /* Rev. 0.3 */ 113 pre = 'M'; m = 1; 114 if (id_str == NULL) 115 id_str = 116 # if defined(CONFIG_MPC852T) 117 "PC852T"; 118 # elif defined(CONFIG_MPC859T) 119 "PC859T"; 120 # elif defined(CONFIG_MPC859DSL) 121 "PC859DSL"; 122 # elif defined(CONFIG_MPC866T) 123 "PC866T"; 124 # else 125 "PC866x"; /* Unknown chip from MPC866 family */ 126 # endif 127 break; 128 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; 129 if (id_str == NULL) 130 id_str = "PC885"; /* 870/875/880/885 */ 131 break; 132 133 default: suf = NULL; break; 134 } 135 136 if (id_str == NULL) 137 id_str = "PC86x"; /* Unknown 86x chip */ 138 if (suf) 139 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); 140 else 141 printf ("unknown M%s (0x%08x)", id_str, k); 142 143 144 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) 145 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", 146 strmhz (buf, clock), 147 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, 148 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, 149 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, 150 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 151 ); 152 #else 153 printf (" at %s MHz: ", strmhz (buf, clock)); 154 #endif 155 printf ("%u kB I-Cache %u kB D-Cache", 156 checkicache () >> 10, 157 checkdcache () >> 10 158 ); 159 160 /* do we have a FEC (860T/P or 852/859/866/885)? */ 161 162 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 163 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 164 printf (" FEC present"); 165 } 166 167 if (!m) { 168 puts (cpu_warning); 169 } 170 171 putc ('\n'); 172 173 #ifdef DEBUG 174 if(clock != measure_gclk()) { 175 printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); 176 } 177 #endif 178 179 return 0; 180 } 181 182 #elif defined(CONFIG_MPC862) 183 184 static int check_CPU (long clock, uint pvr, uint immr) 185 { 186 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 187 uint k, m; 188 char buf[32]; 189 char pre = 'X'; 190 __maybe_unused char *mid = "xx"; 191 char *suf; 192 193 /* the highest 16 bits should be 0x0050 for a 8xx */ 194 195 if ((pvr >> 16) != 0x0050) 196 return -1; 197 198 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 199 m = 0; 200 201 switch (k) { 202 203 /* this value is not documented anywhere */ 204 case 0x06000000: mid = "P"; suf = "0"; break; 205 case 0x06010001: mid = "P"; suf = "A"; m = 1; break; 206 case 0x07000003: mid = "P"; suf = "B"; m = 1; break; 207 default: suf = NULL; break; 208 } 209 210 #ifndef CONFIG_MPC857 211 if (suf) 212 printf ("%cPC862%sZPnn%s", pre, mid, suf); 213 else 214 printf ("unknown MPC862 (0x%08x)", k); 215 #else 216 if (suf) 217 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ 218 else 219 printf ("unknown MPC857 (0x%08x)", k); 220 #endif 221 222 printf (" at %s MHz:", strmhz (buf, clock)); 223 224 printf (" %u kB I-Cache", checkicache () >> 10); 225 printf (" %u kB D-Cache", checkdcache () >> 10); 226 227 /* lets check and see if we're running on a 862T (or P?) */ 228 229 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 230 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 231 printf (" FEC present"); 232 } 233 234 if (!m) { 235 puts (cpu_warning); 236 } 237 238 putc ('\n'); 239 240 return 0; 241 } 242 243 #elif defined(CONFIG_MPC823) 244 245 static int check_CPU (long clock, uint pvr, uint immr) 246 { 247 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 248 uint k, m; 249 char buf[32]; 250 char *suf; 251 252 /* the highest 16 bits should be 0x0050 for a 8xx */ 253 254 if ((pvr >> 16) != 0x0050) 255 return -1; 256 257 k = (immr << 16) | in_be16((ushort *)&immap->im_cpm.cp_dparam[0xB0]); 258 m = 0; 259 260 switch (k) { 261 /* MPC823 */ 262 case 0x20000000: suf = "0"; break; 263 case 0x20010000: suf = "0.1"; break; 264 case 0x20020000: suf = "Z2/3"; break; 265 case 0x20020001: suf = "Z3"; break; 266 case 0x21000000: suf = "A"; break; 267 case 0x21010000: suf = "B"; m = 1; break; 268 case 0x21010001: suf = "B2"; m = 1; break; 269 /* MPC823E */ 270 case 0x24010000: suf = NULL; 271 puts ("PPC823EZTnnB2"); 272 m = 1; 273 break; 274 default: 275 suf = NULL; 276 printf ("unknown MPC823 (0x%08x)", k); 277 break; 278 } 279 if (suf) 280 printf ("PPC823ZTnn%s", suf); 281 282 printf (" at %s MHz:", strmhz (buf, clock)); 283 284 printf (" %u kB I-Cache", checkicache () >> 10); 285 printf (" %u kB D-Cache", checkdcache () >> 10); 286 287 /* lets check and see if we're running on a 860T (or P?) */ 288 289 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 290 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 291 puts (" FEC present"); 292 } 293 294 if (!m) { 295 puts (cpu_warning); 296 } 297 298 putc ('\n'); 299 300 return 0; 301 } 302 303 #elif defined(CONFIG_MPC850) 304 305 static int check_CPU (long clock, uint pvr, uint immr) 306 { 307 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 308 uint k, m; 309 char buf[32]; 310 311 /* the highest 16 bits should be 0x0050 for a 8xx */ 312 313 if ((pvr >> 16) != 0x0050) 314 return -1; 315 316 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); 317 m = 0; 318 319 switch (k) { 320 case 0x20020001: 321 printf ("XPC850xxZT"); 322 break; 323 case 0x21000065: 324 printf ("XPC850xxZTA"); 325 break; 326 case 0x21010067: 327 printf ("XPC850xxZTB"); 328 m = 1; 329 break; 330 case 0x21020068: 331 printf ("XPC850xxZTC"); 332 m = 1; 333 break; 334 default: 335 printf ("unknown MPC850 (0x%08x)", k); 336 } 337 printf (" at %s MHz:", strmhz (buf, clock)); 338 339 printf (" %u kB I-Cache", checkicache () >> 10); 340 printf (" %u kB D-Cache", checkdcache () >> 10); 341 342 /* lets check and see if we're running on a 850T (or P?) */ 343 344 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 345 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 346 printf (" FEC present"); 347 } 348 349 if (!m) { 350 puts (cpu_warning); 351 } 352 353 putc ('\n'); 354 355 return 0; 356 } 357 #else 358 #error CPU undefined 359 #endif 360 /* ------------------------------------------------------------------------- */ 361 362 int checkcpu (void) 363 { 364 ulong clock = gd->cpu_clk; 365 uint immr = get_immr (0); /* Return full IMMR contents */ 366 uint pvr = get_pvr (); 367 368 puts ("CPU: "); 369 370 /* 850 has PARTNUM 20 */ 371 /* 801 has PARTNUM 10 */ 372 return check_CPU (clock, pvr, immr); 373 } 374 375 /* ------------------------------------------------------------------------- */ 376 /* L1 i-cache */ 377 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 378 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ 379 380 int checkicache (void) 381 { 382 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 383 volatile memctl8xx_t *memctl = &immap->im_memctl; 384 u32 cacheon = rd_ic_cst () & IDC_ENABLED; 385 386 #ifdef CONFIG_IP86x 387 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 388 #else 389 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 390 #endif 391 u32 m; 392 u32 lines = -1; 393 394 wr_ic_cst (IDC_UNALL); 395 wr_ic_cst (IDC_INVALL); 396 wr_ic_cst (IDC_DISABLE); 397 __asm__ volatile ("isync"); 398 399 while (!((m = rd_ic_cst ()) & IDC_CERR2)) { 400 wr_ic_adr (k); 401 wr_ic_cst (IDC_LDLCK); 402 __asm__ volatile ("isync"); 403 404 lines++; 405 k += 0x10; /* the number of bytes in a cacheline */ 406 } 407 408 wr_ic_cst (IDC_UNALL); 409 wr_ic_cst (IDC_INVALL); 410 411 if (cacheon) 412 wr_ic_cst (IDC_ENABLE); 413 else 414 wr_ic_cst (IDC_DISABLE); 415 416 __asm__ volatile ("isync"); 417 418 return lines << 4; 419 }; 420 421 /* ------------------------------------------------------------------------- */ 422 /* L1 d-cache */ 423 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 424 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ 425 /* call with cache disabled */ 426 427 int checkdcache (void) 428 { 429 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 430 volatile memctl8xx_t *memctl = &immap->im_memctl; 431 u32 cacheon = rd_dc_cst () & IDC_ENABLED; 432 433 #ifdef CONFIG_IP86x 434 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 435 #else 436 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 437 #endif 438 u32 m; 439 u32 lines = -1; 440 441 wr_dc_cst (IDC_UNALL); 442 wr_dc_cst (IDC_INVALL); 443 wr_dc_cst (IDC_DISABLE); 444 445 while (!((m = rd_dc_cst ()) & IDC_CERR2)) { 446 wr_dc_adr (k); 447 wr_dc_cst (IDC_LDLCK); 448 lines++; 449 k += 0x10; /* the number of bytes in a cacheline */ 450 } 451 452 wr_dc_cst (IDC_UNALL); 453 wr_dc_cst (IDC_INVALL); 454 455 if (cacheon) 456 wr_dc_cst (IDC_ENABLE); 457 else 458 wr_dc_cst (IDC_DISABLE); 459 460 return lines << 4; 461 }; 462 463 /* ------------------------------------------------------------------------- */ 464 465 void upmconfig (uint upm, uint * table, uint size) 466 { 467 uint i; 468 uint addr = 0; 469 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 470 volatile memctl8xx_t *memctl = &immap->im_memctl; 471 472 for (i = 0; i < size; i++) { 473 memctl->memc_mdr = table[i]; /* (16-15) */ 474 memctl->memc_mcr = addr | upm; /* (16-16) */ 475 addr++; 476 } 477 } 478 479 /* ------------------------------------------------------------------------- */ 480 481 #ifndef CONFIG_LWMON 482 483 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 484 { 485 ulong msr, addr; 486 487 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 488 489 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ 490 491 /* Interrupts and MMU off */ 492 __asm__ volatile ("mtspr 81, 0"); 493 __asm__ volatile ("mfmsr %0":"=r" (msr)); 494 495 msr &= ~0x1030; 496 __asm__ volatile ("mtmsr %0"::"r" (msr)); 497 498 /* 499 * Trying to execute the next instruction at a non-existing address 500 * should cause a machine check, resulting in reset 501 */ 502 #ifdef CONFIG_SYS_RESET_ADDRESS 503 addr = CONFIG_SYS_RESET_ADDRESS; 504 #else 505 /* 506 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE 507 * - sizeof (ulong) is usually a valid address. Better pick an address 508 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. 509 * "(ulong)-1" used to be a good choice for many systems... 510 */ 511 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); 512 #endif 513 ((void (*)(void)) addr) (); 514 return 1; 515 } 516 517 #else /* CONFIG_LWMON */ 518 519 /* 520 * On the LWMON board, the MCLR reset input of the PIC's on the board 521 * uses a 47K/1n RC combination which has a 47us time constant. The 522 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us 523 * and thus too short to reset the external hardware. So we use the 524 * watchdog to reset the board. 525 */ 526 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 527 { 528 /* prevent triggering the watchdog */ 529 disable_interrupts (); 530 531 /* make sure the watchdog is running */ 532 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 533 534 /* wait for watchdog reset */ 535 while (1) {}; 536 537 /* NOTREACHED */ 538 return 1; 539 } 540 541 #endif /* CONFIG_LWMON */ 542 543 /* ------------------------------------------------------------------------- */ 544 545 /* 546 * Get timebase clock frequency (like cpu_clk in Hz) 547 * 548 * See sections 14.2 and 14.6 of the User's Manual 549 */ 550 unsigned long get_tbclk (void) 551 { 552 uint immr = get_immr (0); /* Return full IMMR contents */ 553 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); 554 ulong oscclk, factor, pll; 555 556 if (immap->im_clkrst.car_sccr & SCCR_TBS) { 557 return (gd->cpu_clk / 16); 558 } 559 560 pll = immap->im_clkrst.car_plprcr; 561 562 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) 563 564 /* 565 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication 566 * factor is calculated as follows: 567 * 568 * MFN 569 * MFI + ------- 570 * MFD + 1 571 * factor = ----------------- 572 * (PDF + 1) * 2^S 573 * 574 * For older chips, it's just MF field of PLPRCR plus one. 575 */ 576 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ 577 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ 578 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); 579 } else { 580 factor = PLPRCR_val(MF)+1; 581 } 582 583 oscclk = gd->cpu_clk / factor; 584 585 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { 586 return (oscclk / 4); 587 } 588 return (oscclk / 16); 589 } 590 591 /* ------------------------------------------------------------------------- */ 592 593 #if defined(CONFIG_WATCHDOG) 594 void watchdog_reset (void) 595 { 596 int re_enable = disable_interrupts (); 597 598 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 599 if (re_enable) 600 enable_interrupts (); 601 } 602 #endif /* CONFIG_WATCHDOG */ 603 604 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) 605 606 void reset_8xx_watchdog (volatile immap_t * immr) 607 { 608 # if defined(CONFIG_LWMON) 609 /* 610 * The LWMON board uses a MAX6301 Watchdog 611 * with the trigger pin connected to port PA.7 612 * 613 * (The old board version used a MAX706TESA Watchdog, which 614 * had to be handled exactly the same.) 615 */ 616 # define WATCHDOG_BIT 0x0100 617 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 618 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 619 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 620 621 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 622 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 623 /* 624 * The KUP4 boards uses a TPS3705 Watchdog 625 * with the trigger pin connected to port PA.5 626 */ 627 # define WATCHDOG_BIT 0x0400 628 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 629 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 630 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 631 632 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 633 # else 634 /* 635 * All other boards use the MPC8xx Internal Watchdog 636 */ 637 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ 638 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ 639 # endif /* CONFIG_LWMON */ 640 } 641 #endif /* CONFIG_WATCHDOG */ 642 643 /* 644 * Initializes on-chip ethernet controllers. 645 * to override, implement board_eth_init() 646 */ 647 int cpu_eth_init(bd_t *bis) 648 { 649 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET) 650 scc_initialize(bis); 651 #endif 652 #if defined(FEC_ENET) 653 fec_initialize(bis); 654 #endif 655 return 0; 656 } 657