1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * m8xx.c 26 * 27 * CPU specific code 28 * 29 * written or collected and sometimes rewritten by 30 * Magnus Damm <damm@bitsmart.com> 31 * 32 * minor modifications by 33 * Wolfgang Denk <wd@denx.de> 34 */ 35 36 #include <common.h> 37 #include <watchdog.h> 38 #include <command.h> 39 #include <mpc8xx.h> 40 #include <commproc.h> 41 #include <netdev.h> 42 #include <asm/cache.h> 43 #include <linux/compiler.h> 44 #include <asm/io.h> 45 46 #if defined(CONFIG_OF_LIBFDT) 47 #include <libfdt.h> 48 #include <fdt_support.h> 49 #endif 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 static char *cpu_warning = "\n " \ 54 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; 55 56 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ 57 !defined(CONFIG_MPC862)) 58 59 static int check_CPU (long clock, uint pvr, uint immr) 60 { 61 char *id_str = 62 # if defined(CONFIG_MPC855) 63 "PC855"; 64 # elif defined(CONFIG_MPC860P) 65 "PC860P"; 66 # else 67 NULL; 68 # endif 69 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 70 uint k, m; 71 char buf[32]; 72 char pre = 'X'; 73 char *mid = "xx"; 74 char *suf; 75 76 /* the highest 16 bits should be 0x0050 for a 860 */ 77 78 if ((pvr >> 16) != 0x0050) 79 return -1; 80 81 k = (immr << 16) | 82 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; 83 m = 0; 84 suf = ""; 85 86 /* 87 * Some boards use sockets so different CPUs can be used. 88 * We have to check chip version in run time. 89 */ 90 switch (k) { 91 case 0x00020001: pre = 'P'; break; 92 case 0x00030001: break; 93 case 0x00120003: suf = "A"; break; 94 case 0x00130003: suf = "A3"; break; 95 96 case 0x00200004: suf = "B"; break; 97 98 case 0x00300004: suf = "C"; break; 99 case 0x00310004: suf = "C1"; m = 1; break; 100 101 case 0x00200064: mid = "SR"; suf = "B"; break; 102 case 0x00300065: mid = "SR"; suf = "C"; break; 103 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; 104 case 0x05010000: suf = "D3"; m = 1; break; 105 case 0x05020000: suf = "D4"; m = 1; break; 106 /* this value is not documented anywhere */ 107 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; 108 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ 109 case 0x08010004: /* Rev. A.0 */ 110 suf = "A"; 111 /* fall through */ 112 case 0x08000003: /* Rev. 0.3 */ 113 pre = 'M'; m = 1; 114 if (id_str == NULL) 115 id_str = 116 # if defined(CONFIG_MPC852T) 117 "PC852T"; 118 # elif defined(CONFIG_MPC859T) 119 "PC859T"; 120 # elif defined(CONFIG_MPC859DSL) 121 "PC859DSL"; 122 # elif defined(CONFIG_MPC866T) 123 "PC866T"; 124 # else 125 "PC866x"; /* Unknown chip from MPC866 family */ 126 # endif 127 break; 128 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; 129 if (id_str == NULL) 130 id_str = "PC885"; /* 870/875/880/885 */ 131 break; 132 133 default: suf = NULL; break; 134 } 135 136 if (id_str == NULL) 137 id_str = "PC86x"; /* Unknown 86x chip */ 138 if (suf) 139 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); 140 else 141 printf ("unknown M%s (0x%08x)", id_str, k); 142 143 144 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) 145 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", 146 strmhz (buf, clock), 147 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, 148 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, 149 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, 150 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 151 ); 152 #else 153 printf (" at %s MHz: ", strmhz (buf, clock)); 154 #endif 155 printf ("%u kB I-Cache %u kB D-Cache", 156 checkicache () >> 10, 157 checkdcache () >> 10 158 ); 159 160 /* do we have a FEC (860T/P or 852/859/866/885)? */ 161 162 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 163 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 164 printf (" FEC present"); 165 } 166 167 if (!m) { 168 puts (cpu_warning); 169 } 170 171 putc ('\n'); 172 173 #ifdef DEBUG 174 if(clock != measure_gclk()) { 175 printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); 176 } 177 #endif 178 179 return 0; 180 } 181 182 #elif defined(CONFIG_MPC862) 183 184 static int check_CPU (long clock, uint pvr, uint immr) 185 { 186 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 187 uint k, m; 188 char buf[32]; 189 char pre = 'X'; 190 __maybe_unused char *mid = "xx"; 191 char *suf; 192 193 /* the highest 16 bits should be 0x0050 for a 8xx */ 194 195 if ((pvr >> 16) != 0x0050) 196 return -1; 197 198 k = (immr << 16) | 199 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; 200 m = 0; 201 202 switch (k) { 203 204 /* this value is not documented anywhere */ 205 case 0x06000000: mid = "P"; suf = "0"; break; 206 case 0x06010001: mid = "P"; suf = "A"; m = 1; break; 207 case 0x07000003: mid = "P"; suf = "B"; m = 1; break; 208 default: suf = NULL; break; 209 } 210 211 #ifndef CONFIG_MPC857 212 if (suf) 213 printf ("%cPC862%sZPnn%s", pre, mid, suf); 214 else 215 printf ("unknown MPC862 (0x%08x)", k); 216 #else 217 if (suf) 218 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ 219 else 220 printf ("unknown MPC857 (0x%08x)", k); 221 #endif 222 223 printf (" at %s MHz:", strmhz (buf, clock)); 224 225 printf (" %u kB I-Cache", checkicache () >> 10); 226 printf (" %u kB D-Cache", checkdcache () >> 10); 227 228 /* lets check and see if we're running on a 862T (or P?) */ 229 230 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 231 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 232 printf (" FEC present"); 233 } 234 235 if (!m) { 236 puts (cpu_warning); 237 } 238 239 putc ('\n'); 240 241 return 0; 242 } 243 244 #elif defined(CONFIG_MPC823) 245 246 static int check_CPU (long clock, uint pvr, uint immr) 247 { 248 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 249 uint k, m; 250 char buf[32]; 251 char *suf; 252 253 /* the highest 16 bits should be 0x0050 for a 8xx */ 254 255 if ((pvr >> 16) != 0x0050) 256 return -1; 257 258 k = (immr << 16) | 259 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]); 260 m = 0; 261 262 switch (k) { 263 /* MPC823 */ 264 case 0x20000000: suf = "0"; break; 265 case 0x20010000: suf = "0.1"; break; 266 case 0x20020000: suf = "Z2/3"; break; 267 case 0x20020001: suf = "Z3"; break; 268 case 0x21000000: suf = "A"; break; 269 case 0x21010000: suf = "B"; m = 1; break; 270 case 0x21010001: suf = "B2"; m = 1; break; 271 /* MPC823E */ 272 case 0x24010000: suf = NULL; 273 puts ("PPC823EZTnnB2"); 274 m = 1; 275 break; 276 default: 277 suf = NULL; 278 printf ("unknown MPC823 (0x%08x)", k); 279 break; 280 } 281 if (suf) 282 printf ("PPC823ZTnn%s", suf); 283 284 printf (" at %s MHz:", strmhz (buf, clock)); 285 286 printf (" %u kB I-Cache", checkicache () >> 10); 287 printf (" %u kB D-Cache", checkdcache () >> 10); 288 289 /* lets check and see if we're running on a 860T (or P?) */ 290 291 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 292 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 293 puts (" FEC present"); 294 } 295 296 if (!m) { 297 puts (cpu_warning); 298 } 299 300 putc ('\n'); 301 302 return 0; 303 } 304 305 #elif defined(CONFIG_MPC850) 306 307 static int check_CPU (long clock, uint pvr, uint immr) 308 { 309 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); 310 uint k, m; 311 char buf[32]; 312 313 /* the highest 16 bits should be 0x0050 for a 8xx */ 314 315 if ((pvr >> 16) != 0x0050) 316 return -1; 317 318 k = (immr << 16) | 319 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; 320 m = 0; 321 322 switch (k) { 323 case 0x20020001: 324 printf ("XPC850xxZT"); 325 break; 326 case 0x21000065: 327 printf ("XPC850xxZTA"); 328 break; 329 case 0x21010067: 330 printf ("XPC850xxZTB"); 331 m = 1; 332 break; 333 case 0x21020068: 334 printf ("XPC850xxZTC"); 335 m = 1; 336 break; 337 default: 338 printf ("unknown MPC850 (0x%08x)", k); 339 } 340 printf (" at %s MHz:", strmhz (buf, clock)); 341 342 printf (" %u kB I-Cache", checkicache () >> 10); 343 printf (" %u kB D-Cache", checkdcache () >> 10); 344 345 /* lets check and see if we're running on a 850T (or P?) */ 346 347 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; 348 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { 349 printf (" FEC present"); 350 } 351 352 if (!m) { 353 puts (cpu_warning); 354 } 355 356 putc ('\n'); 357 358 return 0; 359 } 360 #else 361 #error CPU undefined 362 #endif 363 /* ------------------------------------------------------------------------- */ 364 365 int checkcpu (void) 366 { 367 ulong clock = gd->cpu_clk; 368 uint immr = get_immr (0); /* Return full IMMR contents */ 369 uint pvr = get_pvr (); 370 371 puts ("CPU: "); 372 373 /* 850 has PARTNUM 20 */ 374 /* 801 has PARTNUM 10 */ 375 return check_CPU (clock, pvr, immr); 376 } 377 378 /* ------------------------------------------------------------------------- */ 379 /* L1 i-cache */ 380 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 381 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ 382 383 int checkicache (void) 384 { 385 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 386 volatile memctl8xx_t *memctl = &immap->im_memctl; 387 u32 cacheon = rd_ic_cst () & IDC_ENABLED; 388 389 #ifdef CONFIG_IP86x 390 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 391 #else 392 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 393 #endif 394 u32 m; 395 u32 lines = -1; 396 397 wr_ic_cst (IDC_UNALL); 398 wr_ic_cst (IDC_INVALL); 399 wr_ic_cst (IDC_DISABLE); 400 __asm__ volatile ("isync"); 401 402 while (!((m = rd_ic_cst ()) & IDC_CERR2)) { 403 wr_ic_adr (k); 404 wr_ic_cst (IDC_LDLCK); 405 __asm__ volatile ("isync"); 406 407 lines++; 408 k += 0x10; /* the number of bytes in a cacheline */ 409 } 410 411 wr_ic_cst (IDC_UNALL); 412 wr_ic_cst (IDC_INVALL); 413 414 if (cacheon) 415 wr_ic_cst (IDC_ENABLE); 416 else 417 wr_ic_cst (IDC_DISABLE); 418 419 __asm__ volatile ("isync"); 420 421 return lines << 4; 422 }; 423 424 /* ------------------------------------------------------------------------- */ 425 /* L1 d-cache */ 426 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ 427 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ 428 /* call with cache disabled */ 429 430 int checkdcache (void) 431 { 432 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 433 volatile memctl8xx_t *memctl = &immap->im_memctl; 434 u32 cacheon = rd_dc_cst () & IDC_ENABLED; 435 436 #ifdef CONFIG_IP86x 437 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ 438 #else 439 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ 440 #endif 441 u32 m; 442 u32 lines = -1; 443 444 wr_dc_cst (IDC_UNALL); 445 wr_dc_cst (IDC_INVALL); 446 wr_dc_cst (IDC_DISABLE); 447 448 while (!((m = rd_dc_cst ()) & IDC_CERR2)) { 449 wr_dc_adr (k); 450 wr_dc_cst (IDC_LDLCK); 451 lines++; 452 k += 0x10; /* the number of bytes in a cacheline */ 453 } 454 455 wr_dc_cst (IDC_UNALL); 456 wr_dc_cst (IDC_INVALL); 457 458 if (cacheon) 459 wr_dc_cst (IDC_ENABLE); 460 else 461 wr_dc_cst (IDC_DISABLE); 462 463 return lines << 4; 464 }; 465 466 /* ------------------------------------------------------------------------- */ 467 468 void upmconfig (uint upm, uint * table, uint size) 469 { 470 uint i; 471 uint addr = 0; 472 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 473 volatile memctl8xx_t *memctl = &immap->im_memctl; 474 475 for (i = 0; i < size; i++) { 476 memctl->memc_mdr = table[i]; /* (16-15) */ 477 memctl->memc_mcr = addr | upm; /* (16-16) */ 478 addr++; 479 } 480 } 481 482 /* ------------------------------------------------------------------------- */ 483 484 #ifndef CONFIG_LWMON 485 486 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 487 { 488 ulong msr, addr; 489 490 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 491 492 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ 493 494 /* Interrupts and MMU off */ 495 __asm__ volatile ("mtspr 81, 0"); 496 __asm__ volatile ("mfmsr %0":"=r" (msr)); 497 498 msr &= ~0x1030; 499 __asm__ volatile ("mtmsr %0"::"r" (msr)); 500 501 /* 502 * Trying to execute the next instruction at a non-existing address 503 * should cause a machine check, resulting in reset 504 */ 505 #ifdef CONFIG_SYS_RESET_ADDRESS 506 addr = CONFIG_SYS_RESET_ADDRESS; 507 #else 508 /* 509 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE 510 * - sizeof (ulong) is usually a valid address. Better pick an address 511 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. 512 * "(ulong)-1" used to be a good choice for many systems... 513 */ 514 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); 515 #endif 516 ((void (*)(void)) addr) (); 517 return 1; 518 } 519 520 #else /* CONFIG_LWMON */ 521 522 /* 523 * On the LWMON board, the MCLR reset input of the PIC's on the board 524 * uses a 47K/1n RC combination which has a 47us time constant. The 525 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us 526 * and thus too short to reset the external hardware. So we use the 527 * watchdog to reset the board. 528 */ 529 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 530 { 531 /* prevent triggering the watchdog */ 532 disable_interrupts (); 533 534 /* make sure the watchdog is running */ 535 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 536 537 /* wait for watchdog reset */ 538 while (1) {}; 539 540 /* NOTREACHED */ 541 return 1; 542 } 543 544 #endif /* CONFIG_LWMON */ 545 546 /* ------------------------------------------------------------------------- */ 547 548 /* 549 * Get timebase clock frequency (like cpu_clk in Hz) 550 * 551 * See sections 14.2 and 14.6 of the User's Manual 552 */ 553 unsigned long get_tbclk (void) 554 { 555 uint immr = get_immr (0); /* Return full IMMR contents */ 556 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); 557 ulong oscclk, factor, pll; 558 559 if (immap->im_clkrst.car_sccr & SCCR_TBS) { 560 return (gd->cpu_clk / 16); 561 } 562 563 pll = immap->im_clkrst.car_plprcr; 564 565 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) 566 567 /* 568 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication 569 * factor is calculated as follows: 570 * 571 * MFN 572 * MFI + ------- 573 * MFD + 1 574 * factor = ----------------- 575 * (PDF + 1) * 2^S 576 * 577 * For older chips, it's just MF field of PLPRCR plus one. 578 */ 579 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ 580 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ 581 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); 582 } else { 583 factor = PLPRCR_val(MF)+1; 584 } 585 586 oscclk = gd->cpu_clk / factor; 587 588 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { 589 return (oscclk / 4); 590 } 591 return (oscclk / 16); 592 } 593 594 /* ------------------------------------------------------------------------- */ 595 596 #if defined(CONFIG_WATCHDOG) 597 void watchdog_reset (void) 598 { 599 int re_enable = disable_interrupts (); 600 601 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); 602 if (re_enable) 603 enable_interrupts (); 604 } 605 #endif /* CONFIG_WATCHDOG */ 606 607 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) 608 609 void reset_8xx_watchdog (volatile immap_t * immr) 610 { 611 # if defined(CONFIG_LWMON) 612 /* 613 * The LWMON board uses a MAX6301 Watchdog 614 * with the trigger pin connected to port PA.7 615 * 616 * (The old board version used a MAX706TESA Watchdog, which 617 * had to be handled exactly the same.) 618 */ 619 # define WATCHDOG_BIT 0x0100 620 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 621 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 622 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 623 624 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 625 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 626 /* 627 * The KUP4 boards uses a TPS3705 Watchdog 628 * with the trigger pin connected to port PA.5 629 */ 630 # define WATCHDOG_BIT 0x0400 631 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ 632 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ 633 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ 634 635 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ 636 # else 637 /* 638 * All other boards use the MPC8xx Internal Watchdog 639 */ 640 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ 641 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ 642 # endif /* CONFIG_LWMON */ 643 } 644 #endif /* CONFIG_WATCHDOG */ 645 646 /* 647 * Initializes on-chip ethernet controllers. 648 * to override, implement board_eth_init() 649 */ 650 int cpu_eth_init(bd_t *bis) 651 { 652 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET) 653 scc_initialize(bis); 654 #endif 655 #if defined(FEC_ENET) 656 fec_initialize(bis); 657 #endif 658 return 0; 659 } 660