1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2002 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * m8xx.c 9 * 10 * CPU specific code 11 * 12 * written or collected and sometimes rewritten by 13 * Magnus Damm <damm@bitsmart.com> 14 * 15 * minor modifications by 16 * Wolfgang Denk <wd@denx.de> 17 */ 18 19 #include <common.h> 20 #include <watchdog.h> 21 #include <command.h> 22 #include <mpc8xx.h> 23 #include <netdev.h> 24 #include <asm/cache.h> 25 #include <asm/cpm_8xx.h> 26 #include <linux/compiler.h> 27 #include <asm/io.h> 28 29 #if defined(CONFIG_OF_LIBFDT) 30 #include <linux/libfdt.h> 31 #include <fdt_support.h> 32 #endif 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static int check_CPU(long clock, uint pvr, uint immr) 37 { 38 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 39 uint k; 40 char buf[32]; 41 42 /* the highest 16 bits should be 0x0050 for a 860 */ 43 44 if (PVR_VER(pvr) != PVR_VER(PVR_8xx)) 45 return -1; 46 47 k = (immr << 16) | 48 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]); 49 50 /* 51 * Some boards use sockets so different CPUs can be used. 52 * We have to check chip version in run time. 53 */ 54 switch (k) { 55 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ 56 case 0x08010004: /* Rev. A.0 */ 57 printf("MPC866xxxZPnnA"); 58 break; 59 case 0x08000003: /* Rev. 0.3 */ 60 printf("MPC866xxxZPnn"); 61 break; 62 case 0x09000000: /* 870/875/880/885 */ 63 puts("MPC885ZPnn"); 64 break; 65 66 default: 67 printf("unknown MPC86x (0x%08x)", k); 68 break; 69 } 70 71 printf(" at %s MHz: ", strmhz(buf, clock)); 72 73 print_size(checkicache(), " I-Cache "); 74 print_size(checkdcache(), " D-Cache"); 75 76 /* do we have a FEC (860T/P or 852/859/866/885)? */ 77 78 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678); 79 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678) 80 printf(" FEC present"); 81 82 putc('\n'); 83 84 return 0; 85 } 86 87 /* ------------------------------------------------------------------------- */ 88 89 int checkcpu(void) 90 { 91 ulong clock = gd->cpu_clk; 92 uint immr = get_immr(); /* Return full IMMR contents */ 93 uint pvr = get_pvr(); 94 95 puts("CPU: "); 96 97 return check_CPU(clock, pvr, immr); 98 } 99 100 /* ------------------------------------------------------------------------- */ 101 /* L1 i-cache */ 102 103 int checkicache(void) 104 { 105 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 106 memctl8xx_t __iomem *memctl = &immap->im_memctl; 107 u32 cacheon = rd_ic_cst() & IDC_ENABLED; 108 /* probe in flash memoryarea */ 109 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; 110 u32 m; 111 u32 lines = -1; 112 113 wr_ic_cst(IDC_UNALL); 114 wr_ic_cst(IDC_INVALL); 115 wr_ic_cst(IDC_DISABLE); 116 __asm__ volatile ("isync"); 117 118 while (!((m = rd_ic_cst()) & IDC_CERR2)) { 119 wr_ic_adr(k); 120 wr_ic_cst(IDC_LDLCK); 121 __asm__ volatile ("isync"); 122 123 lines++; 124 k += 0x10; /* the number of bytes in a cacheline */ 125 } 126 127 wr_ic_cst(IDC_UNALL); 128 wr_ic_cst(IDC_INVALL); 129 130 if (cacheon) 131 wr_ic_cst(IDC_ENABLE); 132 else 133 wr_ic_cst(IDC_DISABLE); 134 135 __asm__ volatile ("isync"); 136 137 return lines << 4; 138 }; 139 140 /* ------------------------------------------------------------------------- */ 141 /* L1 d-cache */ 142 /* call with cache disabled */ 143 144 int checkdcache(void) 145 { 146 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 147 memctl8xx_t __iomem *memctl = &immap->im_memctl; 148 u32 cacheon = rd_dc_cst() & IDC_ENABLED; 149 /* probe in flash memoryarea */ 150 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; 151 u32 m; 152 u32 lines = -1; 153 154 wr_dc_cst(IDC_UNALL); 155 wr_dc_cst(IDC_INVALL); 156 wr_dc_cst(IDC_DISABLE); 157 158 while (!((m = rd_dc_cst()) & IDC_CERR2)) { 159 wr_dc_adr(k); 160 wr_dc_cst(IDC_LDLCK); 161 lines++; 162 k += 0x10; /* the number of bytes in a cacheline */ 163 } 164 165 wr_dc_cst(IDC_UNALL); 166 wr_dc_cst(IDC_INVALL); 167 168 if (cacheon) 169 wr_dc_cst(IDC_ENABLE); 170 else 171 wr_dc_cst(IDC_DISABLE); 172 173 return lines << 4; 174 }; 175 176 /* ------------------------------------------------------------------------- */ 177 178 void upmconfig(uint upm, uint *table, uint size) 179 { 180 uint i; 181 uint addr = 0; 182 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 183 memctl8xx_t __iomem *memctl = &immap->im_memctl; 184 185 for (i = 0; i < size; i++) { 186 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */ 187 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */ 188 addr++; 189 } 190 } 191 192 /* ------------------------------------------------------------------------- */ 193 194 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 195 { 196 ulong msr, addr; 197 198 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 199 200 /* Checkstop Reset enable */ 201 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR); 202 203 /* Interrupts and MMU off */ 204 __asm__ volatile ("mtspr 81, 0"); 205 __asm__ volatile ("mfmsr %0" : "=r" (msr)); 206 207 msr &= ~0x1030; 208 __asm__ volatile ("mtmsr %0" : : "r" (msr)); 209 210 /* 211 * Trying to execute the next instruction at a non-existing address 212 * should cause a machine check, resulting in reset 213 */ 214 #ifdef CONFIG_SYS_RESET_ADDRESS 215 addr = CONFIG_SYS_RESET_ADDRESS; 216 #else 217 /* 218 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, 219 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address. 220 * Better pick an address known to be invalid on your system and assign 221 * it to CONFIG_SYS_RESET_ADDRESS. 222 * "(ulong)-1" used to be a good choice for many systems... 223 */ 224 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); 225 #endif 226 ((void (*)(void)) addr)(); 227 return 1; 228 } 229 230 /* ------------------------------------------------------------------------- */ 231 232 /* 233 * Get timebase clock frequency (like cpu_clk in Hz) 234 * 235 * See sections 14.2 and 14.6 of the User's Manual 236 */ 237 unsigned long get_tbclk(void) 238 { 239 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 240 ulong oscclk, factor, pll; 241 242 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS) 243 return gd->cpu_clk / 16; 244 245 pll = in_be32(&immap->im_clkrst.car_plprcr); 246 247 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) 248 249 /* 250 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication 251 * factor is calculated as follows: 252 * 253 * MFN 254 * MFI + ------- 255 * MFD + 1 256 * factor = ----------------- 257 * (PDF + 1) * 2^S 258 * 259 */ 260 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) / 261 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S)); 262 263 oscclk = gd->cpu_clk / factor; 264 265 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 || 266 factor > 2) 267 return oscclk / 4; 268 269 return oscclk / 16; 270 } 271 272 /* 273 * Initializes on-chip ethernet controllers. 274 * to override, implement board_eth_init() 275 */ 276 int cpu_eth_init(bd_t *bis) 277 { 278 #if defined(CONFIG_MPC8XX_FEC) 279 fec_initialize(bis); 280 #endif 281 return 0; 282 } 283