1/*
2 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7#include <config.h>
8#include <mpc86xx.h>
9#include <version.h>
10
11#include <ppc_asm.tmpl>
12#include <ppc_defs.h>
13
14#include <asm/cache.h>
15#include <asm/mmu.h>
16
17/* If this is a multi-cpu system then we need to handle the
18 * 2nd cpu.  The assumption is that the 2nd cpu is being
19 * held in boot holdoff mode until the 1st cpu unlocks it
20 * from Linux.	We'll do some basic cpu init and then pass
21 * it to the Linux Reset Vector.
22 * Sri:	 Much of this initialization is not required. Linux
23 * rewrites the bats, and the sprs and also enables the L1 cache.
24 *
25 * Core 0 must copy this to a 1M aligned region and set BPTR
26 * to point to it.
27 */
28	.align 12
29.globl __secondary_start_page
30__secondary_start_page:
31	.space 0x100	/* space over to reset vector loc */
32	mfspr	r0, MSSCR0
33	andi.	r0, r0, 0x0020
34	rlwinm	r0,r0,27,31,31
35	mtspr	PIR, r0
36
37	/* Invalidate BATs */
38	li	r0, 0
39	mtspr	IBAT0U, r0
40	mtspr	IBAT1U, r0
41	mtspr	IBAT2U, r0
42	mtspr	IBAT3U, r0
43	mtspr	IBAT4U, r0
44	mtspr	IBAT5U, r0
45	mtspr	IBAT6U, r0
46	mtspr	IBAT7U, r0
47	isync
48	mtspr	DBAT0U, r0
49	mtspr	DBAT1U, r0
50	mtspr	DBAT2U, r0
51	mtspr	DBAT3U, r0
52	mtspr	DBAT4U, r0
53	mtspr	DBAT5U, r0
54	mtspr	DBAT6U, r0
55	mtspr	DBAT7U, r0
56	isync
57	sync
58
59	/* enable extended addressing */
60	mfspr	r0, HID0
61	lis	r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
62	ori	r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
63	mtspr	HID0, r0
64	sync
65	isync
66
67#ifdef CONFIG_SYS_L2
68	/* init the L2 cache */
69	addis	r3, r0, L2_INIT@h
70	ori	r3, r3, L2_INIT@l
71	sync
72	mtspr	l2cr, r3
73#ifdef CONFIG_ALTIVEC
74	dssall
75#endif
76	/* invalidate the L2 cache */
77	mfspr	r3, l2cr
78	rlwinm.	r3, r3, 0, 0, 0
79	beq	1f
80
81	mfspr	r3, l2cr
82	rlwinm	r3, r3, 0, 1, 31
83
84#ifdef	CONFIG_ALTIVEC
85	dssall
86#endif
87	sync
88	mtspr	l2cr, r3
89	sync
901:	mfspr	r3, l2cr
91	oris	r3, r3, L2CR_L2I@h
92	mtspr	l2cr, r3
93
94invl2:
95	mfspr	r3, l2cr
96	andis.	r3, r3, L2CR_L2I@h
97	bne	invl2
98	sync
99#endif
100
101	/* enable and invalidate the data cache */
102	mfspr	r3, HID0
103	li	r5, HID0_DCFI|HID0_DLOCK
104	andc	r3, r3, r5
105	mtspr	HID0, r3		/* no invalidate, unlock */
106	ori	r3, r3, HID0_DCE
107	ori	r5, r3, HID0_DCFI
108	mtspr	HID0, r5		/* enable + invalidate */
109	mtspr	HID0, r3		/* enable */
110	sync
111#ifdef CONFIG_SYS_L2
112	sync
113	lis	r3, L2_ENABLE@h
114	ori	r3, r3, L2_ENABLE@l
115	mtspr	l2cr, r3
116	isync
117	sync
118#endif
119
120	/* enable and invalidate the instruction cache*/
121	mfspr	r3, HID0
122	li	r5, HID0_ICFI|HID0_ILOCK
123	andc	r3, r3, r5
124	ori	r3, r3, HID0_ICE
125	ori	r5, r3, HID0_ICFI
126	mtspr	HID0, r5
127	mtspr	HID0, r3
128	isync
129	sync
130
131	/* TBEN in HID0 */
132	mfspr	r4, HID0
133	oris	r4, r4, 0x0400
134	mtspr	HID0, r4
135	sync
136	isync
137
138	/* MCP|SYNCBE|ABE in HID1 */
139	mfspr	r4, HID1
140	oris	r4, r4, 0x8000
141	ori	r4, r4, 0x0C00
142	mtspr	HID1, r4
143	sync
144	isync
145
146	lis	r3, CONFIG_LINUX_RESET_VEC@h
147	ori	r3, r3, CONFIG_LINUX_RESET_VEC@l
148	mtlr	r3
149	blr
150
151	/* Never Returns, Running in Linux Now */
152