1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <config.h>
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/immap_86xx.h>
11 #include <asm/fsl_serdes.h>
12 
13 #define SRDS1_MAX_LANES		4
14 #define SRDS2_MAX_LANES		4
15 
16 static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17 
18 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19 	[0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
20 	[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
21 	[0x7] = {NONE, NONE, NONE, NONE},
22 };
23 
24 static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
25 	[0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
26 	[0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
27 	[0x7] = {NONE, NONE, NONE, NONE},
28 };
29 
30 int is_serdes_configured(enum srds_prtcl device)
31 {
32 	int ret = (1 << device) & serdes1_prtcl_map;
33 
34 	if (ret)
35 		return ret;
36 
37 	return (1 << device) & serdes2_prtcl_map;
38 }
39 
40 void fsl_serdes_init(void)
41 {
42 	immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
43 	ccsr_gur_t *gur = &immap->im_gur;
44 	u32 pordevsr = in_be32(&gur->pordevsr);
45 	u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
46 				MPC8610_PORDEVSR_IO_SEL_SHIFT;
47 	int lane;
48 
49 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
50 
51 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
52 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
53 		return;
54 	}
55 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
56 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
57 		serdes1_prtcl_map |= (1 << lane_prtcl);
58 	}
59 
60 	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
61 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
62 		return;
63 	}
64 
65 	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
66 		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
67 		serdes2_prtcl_map |= (1 << lane_prtcl);
68 	}
69 }
70