1 /* 2 * Copyright 2004,2009 Freescale Semiconductor, Inc. 3 * Jeff Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * cpu_init.c - low level cpu init 27 */ 28 29 #include <config.h> 30 #include <common.h> 31 #include <mpc86xx.h> 32 #include <asm/mmu.h> 33 #include <asm/fsl_law.h> 34 #include <asm/mp.h> 35 36 void setup_bats(void); 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 /* 41 * Breathe some life into the CPU... 42 * 43 * Set up the memory map 44 * initialize a bunch of registers 45 */ 46 47 void cpu_init_f(void) 48 { 49 /* Pointer is writable since we allocated a register for it */ 50 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 51 52 /* Clear initial global data */ 53 memset ((void *) gd, 0, sizeof (gd_t)); 54 55 #ifdef CONFIG_FSL_LAW 56 init_laws(); 57 #endif 58 59 setup_bats(); 60 61 init_early_memctl_regs(); 62 63 #if defined(CONFIG_FSL_DMA) 64 dma_init(); 65 #endif 66 67 /* enable the timebase bit in HID0 */ 68 set_hid0(get_hid0() | 0x4000000); 69 70 /* enable EMCP, SYNCBE | ABE bits in HID1 */ 71 set_hid1(get_hid1() | 0x80000C00); 72 } 73 74 /* 75 * initialize higher level parts of CPU like timers 76 */ 77 int cpu_init_r(void) 78 { 79 #if defined(CONFIG_MP) 80 setup_mp(); 81 #endif 82 return 0; 83 } 84 85 /* Set up BAT registers */ 86 void setup_bats(void) 87 { 88 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) 89 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); 90 #endif 91 #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 92 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); 93 #endif 94 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); 95 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); 96 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); 97 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); 98 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); 99 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); 100 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); 101 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); 102 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); 103 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); 104 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); 105 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); 106 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); 107 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); 108 109 return; 110 } 111 112 #ifdef CONFIG_ADDR_MAP 113 /* Initialize address mapping array */ 114 void init_addr_map(void) 115 { 116 int i; 117 ppc_bat_t bat = DBAT0; 118 phys_size_t size; 119 unsigned long upper, lower; 120 121 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { 122 if (read_bat(bat, &upper, &lower) != -1) { 123 if (!BATU_VALID(upper)) 124 size = 0; 125 else 126 size = BATU_SIZE(upper); 127 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 128 size, i); 129 } 130 #ifdef CONFIG_HIGH_BATS 131 /* High bats are not contiguous with low BAT numbers */ 132 if (bat == DBAT3) 133 bat = DBAT4 - 1; 134 #endif 135 } 136 } 137 #endif 138