1 /* 2 * Copyright 2004,2009 Freescale Semiconductor, Inc. 3 * Jeff Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * cpu_init.c - low level cpu init 27 */ 28 29 #include <config.h> 30 #include <common.h> 31 #include <mpc86xx.h> 32 #include <asm/mmu.h> 33 #include <asm/fsl_law.h> 34 #include <asm/mp.h> 35 36 void setup_bats(void); 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 /* 41 * Breathe some life into the CPU... 42 * 43 * Set up the memory map 44 * initialize a bunch of registers 45 */ 46 47 void cpu_init_f(void) 48 { 49 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 50 volatile ccsr_lbc_t *memctl = &immap->im_lbc; 51 52 /* Pointer is writable since we allocated a register for it */ 53 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 54 55 /* Clear initial global data */ 56 memset ((void *) gd, 0, sizeof (gd_t)); 57 58 #ifdef CONFIG_FSL_LAW 59 init_laws(); 60 #endif 61 62 setup_bats(); 63 64 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 65 * addresses - these have to be modified later when FLASH size 66 * has been determined 67 */ 68 69 #if defined(CONFIG_SYS_OR0_REMAP) 70 memctl->or0 = CONFIG_SYS_OR0_REMAP; 71 #endif 72 #if defined(CONFIG_SYS_OR1_REMAP) 73 memctl->or1 = CONFIG_SYS_OR1_REMAP; 74 #endif 75 76 /* now restrict to preliminary range */ 77 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) 78 memctl->br0 = CONFIG_SYS_BR0_PRELIM; 79 memctl->or0 = CONFIG_SYS_OR0_PRELIM; 80 #endif 81 82 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) 83 memctl->or1 = CONFIG_SYS_OR1_PRELIM; 84 memctl->br1 = CONFIG_SYS_BR1_PRELIM; 85 #endif 86 87 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) 88 memctl->or2 = CONFIG_SYS_OR2_PRELIM; 89 memctl->br2 = CONFIG_SYS_BR2_PRELIM; 90 #endif 91 92 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) 93 memctl->or3 = CONFIG_SYS_OR3_PRELIM; 94 memctl->br3 = CONFIG_SYS_BR3_PRELIM; 95 #endif 96 97 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) 98 memctl->or4 = CONFIG_SYS_OR4_PRELIM; 99 memctl->br4 = CONFIG_SYS_BR4_PRELIM; 100 #endif 101 102 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) 103 memctl->or5 = CONFIG_SYS_OR5_PRELIM; 104 memctl->br5 = CONFIG_SYS_BR5_PRELIM; 105 #endif 106 107 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) 108 memctl->or6 = CONFIG_SYS_OR6_PRELIM; 109 memctl->br6 = CONFIG_SYS_BR6_PRELIM; 110 #endif 111 112 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) 113 memctl->or7 = CONFIG_SYS_OR7_PRELIM; 114 memctl->br7 = CONFIG_SYS_BR7_PRELIM; 115 #endif 116 #if defined(CONFIG_FSL_DMA) 117 dma_init(); 118 #endif 119 120 /* enable the timebase bit in HID0 */ 121 set_hid0(get_hid0() | 0x4000000); 122 123 /* enable EMCP, SYNCBE | ABE bits in HID1 */ 124 set_hid1(get_hid1() | 0x80000C00); 125 } 126 127 /* 128 * initialize higher level parts of CPU like timers 129 */ 130 int cpu_init_r(void) 131 { 132 #if defined(CONFIG_MP) 133 setup_mp(); 134 #endif 135 return 0; 136 } 137 138 /* Set up BAT registers */ 139 void setup_bats(void) 140 { 141 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) 142 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); 143 #endif 144 #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 145 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); 146 #endif 147 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); 148 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); 149 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); 150 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); 151 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); 152 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); 153 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); 154 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); 155 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); 156 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); 157 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); 158 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); 159 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); 160 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); 161 162 return; 163 } 164 165 #ifdef CONFIG_ADDR_MAP 166 /* Initialize address mapping array */ 167 void init_addr_map(void) 168 { 169 int i; 170 ppc_bat_t bat = DBAT0; 171 phys_size_t size; 172 unsigned long upper, lower; 173 174 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { 175 if (read_bat(bat, &upper, &lower) != -1) { 176 if (!BATU_VALID(upper)) 177 size = 0; 178 else 179 size = BATU_SIZE(upper); 180 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 181 size, i); 182 } 183 #ifdef CONFIG_HIGH_BATS 184 /* High bats are not contiguous with low BAT numbers */ 185 if (bat == DBAT3) 186 bat = DBAT4 - 1; 187 #endif 188 } 189 } 190 #endif 191