1 /* 2 * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. 3 * Jeff Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * cpu_init.c - low level cpu init 27 */ 28 29 #include <config.h> 30 #include <common.h> 31 #include <mpc86xx.h> 32 #include <asm/mmu.h> 33 #include <asm/fsl_law.h> 34 #include <asm/fsl_serdes.h> 35 #include <asm/mp.h> 36 37 extern void srio_init(void); 38 void setup_bats(void); 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* 43 * Breathe some life into the CPU... 44 * 45 * Set up the memory map 46 * initialize a bunch of registers 47 */ 48 49 void cpu_init_f(void) 50 { 51 /* Pointer is writable since we allocated a register for it */ 52 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 53 54 /* Clear initial global data */ 55 memset ((void *) gd, 0, sizeof (gd_t)); 56 57 #ifdef CONFIG_FSL_LAW 58 init_laws(); 59 #endif 60 61 setup_bats(); 62 63 init_early_memctl_regs(); 64 65 #if defined(CONFIG_FSL_DMA) 66 dma_init(); 67 #endif 68 69 /* enable the timebase bit in HID0 */ 70 set_hid0(get_hid0() | 0x4000000); 71 72 /* enable EMCP, SYNCBE | ABE bits in HID1 */ 73 set_hid1(get_hid1() | 0x80000C00); 74 } 75 76 /* 77 * initialize higher level parts of CPU like timers 78 */ 79 int cpu_init_r(void) 80 { 81 /* needs to be in ram since code uses global static vars */ 82 fsl_serdes_init(); 83 84 #ifdef CONFIG_SYS_SRIO 85 srio_init(); 86 #endif 87 88 #if defined(CONFIG_MP) 89 setup_mp(); 90 #endif 91 return 0; 92 } 93 94 /* Set up BAT registers */ 95 void setup_bats(void) 96 { 97 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) 98 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); 99 #endif 100 #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 101 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); 102 #endif 103 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); 104 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); 105 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); 106 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); 107 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); 108 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); 109 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); 110 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); 111 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); 112 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); 113 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); 114 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); 115 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); 116 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); 117 118 return; 119 } 120 121 #ifdef CONFIG_ADDR_MAP 122 /* Initialize address mapping array */ 123 void init_addr_map(void) 124 { 125 int i; 126 ppc_bat_t bat = DBAT0; 127 phys_size_t size; 128 unsigned long upper, lower; 129 130 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { 131 if (read_bat(bat, &upper, &lower) != -1) { 132 if (!BATU_VALID(upper)) 133 size = 0; 134 else 135 size = BATU_SIZE(upper); 136 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 137 size, i); 138 } 139 #ifdef CONFIG_HIGH_BATS 140 /* High bats are not contiguous with low BAT numbers */ 141 if (bat == DBAT3) 142 bat = DBAT4 - 1; 143 #endif 144 } 145 } 146 #endif 147