1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a47a12beSStefan Roese /* 356551362SKumar Gala * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. 4a47a12beSStefan Roese * Jeff Brown 5a47a12beSStefan Roese * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese /* 9a47a12beSStefan Roese * cpu_init.c - low level cpu init 10a47a12beSStefan Roese */ 11a47a12beSStefan Roese 12a47a12beSStefan Roese #include <config.h> 13a47a12beSStefan Roese #include <common.h> 14a47a12beSStefan Roese #include <mpc86xx.h> 15a47a12beSStefan Roese #include <asm/mmu.h> 16a47a12beSStefan Roese #include <asm/fsl_law.h> 17af042474SKumar Gala #include <asm/fsl_serdes.h> 18a47a12beSStefan Roese #include <asm/mp.h> 19a47a12beSStefan Roese 2056551362SKumar Gala extern void srio_init(void); 21a47a12beSStefan Roese 22a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 23a47a12beSStefan Roese 24a47a12beSStefan Roese /* 25a47a12beSStefan Roese * Breathe some life into the CPU... 26a47a12beSStefan Roese * 27a47a12beSStefan Roese * Set up the memory map 28a47a12beSStefan Roese * initialize a bunch of registers 29a47a12beSStefan Roese */ 30a47a12beSStefan Roese 31a47a12beSStefan Roese void cpu_init_f(void) 32a47a12beSStefan Roese { 33a47a12beSStefan Roese /* Pointer is writable since we allocated a register for it */ 34a47a12beSStefan Roese gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 35a47a12beSStefan Roese 36a47a12beSStefan Roese /* Clear initial global data */ 37a47a12beSStefan Roese memset ((void *) gd, 0, sizeof (gd_t)); 38a47a12beSStefan Roese 39a47a12beSStefan Roese #ifdef CONFIG_FSL_LAW 40a47a12beSStefan Roese init_laws(); 41a47a12beSStefan Roese #endif 42a47a12beSStefan Roese 43a47a12beSStefan Roese setup_bats(); 44a47a12beSStefan Roese 45f51cdaf1SBecky Bruce init_early_memctl_regs(); 46a47a12beSStefan Roese 47a47a12beSStefan Roese #if defined(CONFIG_FSL_DMA) 48a47a12beSStefan Roese dma_init(); 49a47a12beSStefan Roese #endif 50a47a12beSStefan Roese 51a47a12beSStefan Roese /* enable the timebase bit in HID0 */ 52a47a12beSStefan Roese set_hid0(get_hid0() | 0x4000000); 53a47a12beSStefan Roese 54a47a12beSStefan Roese /* enable EMCP, SYNCBE | ABE bits in HID1 */ 55a47a12beSStefan Roese set_hid1(get_hid1() | 0x80000C00); 56a47a12beSStefan Roese } 57a47a12beSStefan Roese 58a47a12beSStefan Roese /* 59a47a12beSStefan Roese * initialize higher level parts of CPU like timers 60a47a12beSStefan Roese */ 61a47a12beSStefan Roese int cpu_init_r(void) 62a47a12beSStefan Roese { 63af042474SKumar Gala /* needs to be in ram since code uses global static vars */ 64af042474SKumar Gala fsl_serdes_init(); 65af042474SKumar Gala 6656551362SKumar Gala #ifdef CONFIG_SYS_SRIO 6756551362SKumar Gala srio_init(); 6856551362SKumar Gala #endif 6956551362SKumar Gala 70a47a12beSStefan Roese #if defined(CONFIG_MP) 71a47a12beSStefan Roese setup_mp(); 72a47a12beSStefan Roese #endif 73a47a12beSStefan Roese return 0; 74a47a12beSStefan Roese } 75a47a12beSStefan Roese 76a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP 77a47a12beSStefan Roese /* Initialize address mapping array */ 78a47a12beSStefan Roese void init_addr_map(void) 79a47a12beSStefan Roese { 80a47a12beSStefan Roese int i; 81a47a12beSStefan Roese ppc_bat_t bat = DBAT0; 82a47a12beSStefan Roese phys_size_t size; 83a47a12beSStefan Roese unsigned long upper, lower; 84a47a12beSStefan Roese 85a47a12beSStefan Roese for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { 86a47a12beSStefan Roese if (read_bat(bat, &upper, &lower) != -1) { 87a47a12beSStefan Roese if (!BATU_VALID(upper)) 88a47a12beSStefan Roese size = 0; 89a47a12beSStefan Roese else 90a47a12beSStefan Roese size = BATU_SIZE(upper); 91a47a12beSStefan Roese addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 92a47a12beSStefan Roese size, i); 93a47a12beSStefan Roese } 94a47a12beSStefan Roese #ifdef CONFIG_HIGH_BATS 95a47a12beSStefan Roese /* High bats are not contiguous with low BAT numbers */ 96a47a12beSStefan Roese if (bat == DBAT3) 97a47a12beSStefan Roese bat = DBAT4 - 1; 98a47a12beSStefan Roese #endif 99a47a12beSStefan Roese } 100a47a12beSStefan Roese } 101a47a12beSStefan Roese #endif 102