1a47a12beSStefan Roese /* 2*56551362SKumar Gala * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * Jeff Brown 4a47a12beSStefan Roese * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5a47a12beSStefan Roese * 6a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 7a47a12beSStefan Roese * project. 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 10a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 11a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 12a47a12beSStefan Roese * the License, or (at your option) any later version. 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 15a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 16a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17a47a12beSStefan Roese * GNU General Public License for more details. 18a47a12beSStefan Roese * 19a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 20a47a12beSStefan Roese * along with this program; if not, write to the Free Software 21a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22a47a12beSStefan Roese * MA 02111-1307 USA 23a47a12beSStefan Roese */ 24a47a12beSStefan Roese 25a47a12beSStefan Roese /* 26a47a12beSStefan Roese * cpu_init.c - low level cpu init 27a47a12beSStefan Roese */ 28a47a12beSStefan Roese 29a47a12beSStefan Roese #include <config.h> 30a47a12beSStefan Roese #include <common.h> 31a47a12beSStefan Roese #include <mpc86xx.h> 32a47a12beSStefan Roese #include <asm/mmu.h> 33a47a12beSStefan Roese #include <asm/fsl_law.h> 34af042474SKumar Gala #include <asm/fsl_serdes.h> 35a47a12beSStefan Roese #include <asm/mp.h> 36a47a12beSStefan Roese 37*56551362SKumar Gala extern void srio_init(void); 38a47a12beSStefan Roese void setup_bats(void); 39a47a12beSStefan Roese 40a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 41a47a12beSStefan Roese 42a47a12beSStefan Roese /* 43a47a12beSStefan Roese * Breathe some life into the CPU... 44a47a12beSStefan Roese * 45a47a12beSStefan Roese * Set up the memory map 46a47a12beSStefan Roese * initialize a bunch of registers 47a47a12beSStefan Roese */ 48a47a12beSStefan Roese 49a47a12beSStefan Roese void cpu_init_f(void) 50a47a12beSStefan Roese { 51a47a12beSStefan Roese /* Pointer is writable since we allocated a register for it */ 52a47a12beSStefan Roese gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 53a47a12beSStefan Roese 54a47a12beSStefan Roese /* Clear initial global data */ 55a47a12beSStefan Roese memset ((void *) gd, 0, sizeof (gd_t)); 56a47a12beSStefan Roese 57a47a12beSStefan Roese #ifdef CONFIG_FSL_LAW 58a47a12beSStefan Roese init_laws(); 59a47a12beSStefan Roese #endif 60a47a12beSStefan Roese 61a47a12beSStefan Roese setup_bats(); 62a47a12beSStefan Roese 63f51cdaf1SBecky Bruce init_early_memctl_regs(); 64a47a12beSStefan Roese 65a47a12beSStefan Roese #if defined(CONFIG_FSL_DMA) 66a47a12beSStefan Roese dma_init(); 67a47a12beSStefan Roese #endif 68a47a12beSStefan Roese 69a47a12beSStefan Roese /* enable the timebase bit in HID0 */ 70a47a12beSStefan Roese set_hid0(get_hid0() | 0x4000000); 71a47a12beSStefan Roese 72a47a12beSStefan Roese /* enable EMCP, SYNCBE | ABE bits in HID1 */ 73a47a12beSStefan Roese set_hid1(get_hid1() | 0x80000C00); 74a47a12beSStefan Roese } 75a47a12beSStefan Roese 76a47a12beSStefan Roese /* 77a47a12beSStefan Roese * initialize higher level parts of CPU like timers 78a47a12beSStefan Roese */ 79a47a12beSStefan Roese int cpu_init_r(void) 80a47a12beSStefan Roese { 81af042474SKumar Gala /* needs to be in ram since code uses global static vars */ 82af042474SKumar Gala fsl_serdes_init(); 83af042474SKumar Gala 84*56551362SKumar Gala #ifdef CONFIG_SYS_SRIO 85*56551362SKumar Gala srio_init(); 86*56551362SKumar Gala #endif 87*56551362SKumar Gala 88a47a12beSStefan Roese #if defined(CONFIG_MP) 89a47a12beSStefan Roese setup_mp(); 90a47a12beSStefan Roese #endif 91a47a12beSStefan Roese return 0; 92a47a12beSStefan Roese } 93a47a12beSStefan Roese 94a47a12beSStefan Roese /* Set up BAT registers */ 95a47a12beSStefan Roese void setup_bats(void) 96a47a12beSStefan Roese { 97a47a12beSStefan Roese #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) 98a47a12beSStefan Roese write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); 99a47a12beSStefan Roese #endif 100a47a12beSStefan Roese #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 101a47a12beSStefan Roese write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); 102a47a12beSStefan Roese #endif 103a47a12beSStefan Roese write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); 104a47a12beSStefan Roese write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); 105a47a12beSStefan Roese write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); 106a47a12beSStefan Roese write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); 107a47a12beSStefan Roese write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); 108a47a12beSStefan Roese write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); 109a47a12beSStefan Roese write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); 110a47a12beSStefan Roese write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); 111a47a12beSStefan Roese write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); 112a47a12beSStefan Roese write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); 113a47a12beSStefan Roese write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); 114a47a12beSStefan Roese write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); 115a47a12beSStefan Roese write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); 116a47a12beSStefan Roese write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); 117a47a12beSStefan Roese 118a47a12beSStefan Roese return; 119a47a12beSStefan Roese } 120a47a12beSStefan Roese 121a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP 122a47a12beSStefan Roese /* Initialize address mapping array */ 123a47a12beSStefan Roese void init_addr_map(void) 124a47a12beSStefan Roese { 125a47a12beSStefan Roese int i; 126a47a12beSStefan Roese ppc_bat_t bat = DBAT0; 127a47a12beSStefan Roese phys_size_t size; 128a47a12beSStefan Roese unsigned long upper, lower; 129a47a12beSStefan Roese 130a47a12beSStefan Roese for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { 131a47a12beSStefan Roese if (read_bat(bat, &upper, &lower) != -1) { 132a47a12beSStefan Roese if (!BATU_VALID(upper)) 133a47a12beSStefan Roese size = 0; 134a47a12beSStefan Roese else 135a47a12beSStefan Roese size = BATU_SIZE(upper); 136a47a12beSStefan Roese addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 137a47a12beSStefan Roese size, i); 138a47a12beSStefan Roese } 139a47a12beSStefan Roese #ifdef CONFIG_HIGH_BATS 140a47a12beSStefan Roese /* High bats are not contiguous with low BAT numbers */ 141a47a12beSStefan Roese if (bat == DBAT3) 142a47a12beSStefan Roese bat = DBAT4 - 1; 143a47a12beSStefan Roese #endif 144a47a12beSStefan Roese } 145a47a12beSStefan Roese } 146a47a12beSStefan Roese #endif 147