1 /* 2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. 3 * Jeff Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <watchdog.h> 27 #include <command.h> 28 #include <asm/cache.h> 29 #include <asm/mmu.h> 30 #include <mpc86xx.h> 31 #include <asm/fsl_law.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* 36 * Default board reset function 37 */ 38 static void 39 __board_reset(void) 40 { 41 /* Do nothing */ 42 } 43 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 44 45 46 int 47 checkcpu(void) 48 { 49 sys_info_t sysinfo; 50 uint pvr, svr; 51 uint major, minor; 52 char buf1[32], buf2[32]; 53 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 54 volatile ccsr_gur_t *gur = &immap->im_gur; 55 struct cpu_type *cpu; 56 uint msscr0 = mfspr(MSSCR0); 57 58 svr = get_svr(); 59 major = SVR_MAJ(svr); 60 minor = SVR_MIN(svr); 61 62 if (cpu_numcores() > 1) { 63 #ifndef CONFIG_MP 64 puts("Unicore software on multiprocessor system!!\n" 65 "To enable mutlticore build define CONFIG_MP\n"); 66 #endif 67 } 68 puts("CPU: "); 69 70 cpu = gd->cpu; 71 72 puts(cpu->name); 73 74 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 75 puts("Core: "); 76 77 pvr = get_pvr(); 78 major = PVR_E600_MAJ(pvr); 79 minor = PVR_E600_MIN(pvr); 80 81 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); 82 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) 83 puts("\n Core1Translation Enabled"); 84 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); 85 86 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 87 88 get_sys_info(&sysinfo); 89 90 puts("Clock Configuration:\n"); 91 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); 92 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 93 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 94 strmhz(buf1, sysinfo.freqSystemBus / 2), 95 strmhz(buf2, sysinfo.freqSystemBus)); 96 97 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 98 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 99 } else { 100 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 101 sysinfo.freqLocalBus); 102 } 103 104 puts("L1: D-cache 32 KB enabled\n"); 105 puts(" I-cache 32 KB enabled\n"); 106 107 puts("L2: "); 108 if (get_l2cr() & 0x80000000) { 109 #if defined(CONFIG_MPC8610) 110 puts("256"); 111 #elif defined(CONFIG_MPC8641) 112 puts("512"); 113 #endif 114 puts(" KB enabled\n"); 115 } else { 116 puts("Disabled\n"); 117 } 118 119 return 0; 120 } 121 122 123 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 124 { 125 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 126 volatile ccsr_gur_t *gur = &immap->im_gur; 127 128 /* Attempt board-specific reset */ 129 board_reset(); 130 131 /* Next try asserting HRESET_REQ */ 132 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); 133 134 while (1) 135 ; 136 137 return 1; 138 } 139 140 141 /* 142 * Get timebase clock frequency 143 */ 144 unsigned long 145 get_tbclk(void) 146 { 147 sys_info_t sys_info; 148 149 get_sys_info(&sys_info); 150 return (sys_info.freqSystemBus + 3L) / 4L; 151 } 152 153 154 #if defined(CONFIG_WATCHDOG) 155 void 156 watchdog_reset(void) 157 { 158 #if defined(CONFIG_MPC8610) 159 /* 160 * This actually feed the hard enabled watchdog. 161 */ 162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 163 volatile ccsr_wdt_t *wdt = &immap->im_wdt; 164 volatile ccsr_gur_t *gur = &immap->im_gur; 165 u32 tmp = gur->pordevsr; 166 167 if (tmp & 0x4000) { 168 wdt->swsrr = 0x556c; 169 wdt->swsrr = 0xaa39; 170 } 171 #endif 172 } 173 #endif /* CONFIG_WATCHDOG */ 174 175 /* 176 * Print out the state of various machine registers. 177 * Currently prints out LAWs, BR0/OR0, and BATs 178 */ 179 void mpc86xx_reginfo(void) 180 { 181 print_bats(); 182 print_laws(); 183 print_lbc_regs(); 184 } 185 186 /* 187 * Set the DDR BATs to reflect the actual size of DDR. 188 * 189 * dram_size is the actual size of DDR, in bytes 190 * 191 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only 192 * are using a single BAT to cover DDR. 193 * 194 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN 195 * is not defined) then we might have a situation where U-Boot will attempt 196 * to relocated itself outside of the region mapped by DBAT0. 197 * This will cause a machine check. 198 * 199 * Currently we are limited to power of two sized DDR since we only use a 200 * single bat. If a non-power of two size is used that is less than 201 * CONFIG_MAX_MEM_MAPPED u-boot will crash. 202 * 203 */ 204 void setup_ddr_bat(phys_addr_t dram_size) 205 { 206 unsigned long batu, bl; 207 208 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); 209 210 if (BATU_SIZE(bl) != dram_size) { 211 u64 sz = (u64)dram_size - BATU_SIZE(bl); 212 print_size(sz, " left unmapped\n"); 213 } 214 215 batu = bl | BATU_VS | BATU_VP; 216 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); 217 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); 218 } 219