1 /* 2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. 3 * Jeff Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <watchdog.h> 27 #include <command.h> 28 #include <asm/cache.h> 29 #include <asm/mmu.h> 30 #include <mpc86xx.h> 31 #include <asm/fsl_law.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* 36 * Default board reset function 37 */ 38 static void 39 __board_reset(void) 40 { 41 /* Do nothing */ 42 } 43 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 44 45 46 int 47 checkcpu(void) 48 { 49 sys_info_t sysinfo; 50 uint pvr, svr; 51 uint ver; 52 uint major, minor; 53 char buf1[32], buf2[32]; 54 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 55 volatile ccsr_gur_t *gur = &immap->im_gur; 56 struct cpu_type *cpu; 57 uint msscr0 = mfspr(MSSCR0); 58 59 svr = get_svr(); 60 ver = SVR_SOC_VER(svr); 61 major = SVR_MAJ(svr); 62 minor = SVR_MIN(svr); 63 64 if (cpu_numcores() > 1) { 65 #ifndef CONFIG_MP 66 puts("Unicore software on multiprocessor system!!\n" 67 "To enable mutlticore build define CONFIG_MP\n"); 68 #endif 69 } 70 puts("CPU: "); 71 72 cpu = gd->cpu; 73 74 puts(cpu->name); 75 76 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 77 puts("Core: "); 78 79 pvr = get_pvr(); 80 ver = PVR_E600_VER(pvr); 81 major = PVR_E600_MAJ(pvr); 82 minor = PVR_E600_MIN(pvr); 83 84 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); 85 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) 86 puts("\n Core1Translation Enabled"); 87 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); 88 89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 90 91 get_sys_info(&sysinfo); 92 93 puts("Clock Configuration:\n"); 94 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); 95 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 96 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 97 strmhz(buf1, sysinfo.freqSystemBus / 2), 98 strmhz(buf2, sysinfo.freqSystemBus)); 99 100 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 101 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 102 } else { 103 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 104 sysinfo.freqLocalBus); 105 } 106 107 puts("L1: D-cache 32 KB enabled\n"); 108 puts(" I-cache 32 KB enabled\n"); 109 110 puts("L2: "); 111 if (get_l2cr() & 0x80000000) { 112 #if defined(CONFIG_MPC8610) 113 puts("256"); 114 #elif defined(CONFIG_MPC8641) 115 puts("512"); 116 #endif 117 puts(" KB enabled\n"); 118 } else { 119 puts("Disabled\n"); 120 } 121 122 return 0; 123 } 124 125 126 void 127 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 128 { 129 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 130 volatile ccsr_gur_t *gur = &immap->im_gur; 131 132 /* Attempt board-specific reset */ 133 board_reset(); 134 135 /* Next try asserting HRESET_REQ */ 136 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); 137 138 while (1) 139 ; 140 } 141 142 143 /* 144 * Get timebase clock frequency 145 */ 146 unsigned long 147 get_tbclk(void) 148 { 149 sys_info_t sys_info; 150 151 get_sys_info(&sys_info); 152 return (sys_info.freqSystemBus + 3L) / 4L; 153 } 154 155 156 #if defined(CONFIG_WATCHDOG) 157 void 158 watchdog_reset(void) 159 { 160 #if defined(CONFIG_MPC8610) 161 /* 162 * This actually feed the hard enabled watchdog. 163 */ 164 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 165 volatile ccsr_wdt_t *wdt = &immap->im_wdt; 166 volatile ccsr_gur_t *gur = &immap->im_gur; 167 u32 tmp = gur->pordevsr; 168 169 if (tmp & 0x4000) { 170 wdt->swsrr = 0x556c; 171 wdt->swsrr = 0xaa39; 172 } 173 #endif 174 } 175 #endif /* CONFIG_WATCHDOG */ 176 177 /* 178 * Print out the state of various machine registers. 179 * Currently prints out LAWs, BR0/OR0, and BATs 180 */ 181 void mpc86xx_reginfo(void) 182 { 183 print_bats(); 184 print_laws(); 185 print_lbc_regs(); 186 } 187 188 /* 189 * Set the DDR BATs to reflect the actual size of DDR. 190 * 191 * dram_size is the actual size of DDR, in bytes 192 * 193 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only 194 * are using a single BAT to cover DDR. 195 * 196 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN 197 * is not defined) then we might have a situation where U-Boot will attempt 198 * to relocated itself outside of the region mapped by DBAT0. 199 * This will cause a machine check. 200 * 201 * Currently we are limited to power of two sized DDR since we only use a 202 * single bat. If a non-power of two size is used that is less than 203 * CONFIG_MAX_MEM_MAPPED u-boot will crash. 204 * 205 */ 206 void setup_ddr_bat(phys_addr_t dram_size) 207 { 208 unsigned long batu, bl; 209 210 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); 211 212 if (BATU_SIZE(bl) != dram_size) { 213 u64 sz = (u64)dram_size - BATU_SIZE(bl); 214 print_size(sz, " left unmapped\n"); 215 } 216 217 batu = bl | BATU_VS | BATU_VP; 218 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); 219 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); 220 } 221