1/*
2 * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include "config.h"	/* CONFIG_BOARDDIR */
8
9#ifdef CONFIG_RESET_VECTOR_ADDRESS
10#define RESET_VECTOR_ADDRESS	CONFIG_RESET_VECTOR_ADDRESS
11#else
12#define RESET_VECTOR_ADDRESS	0xfffffffc
13#endif
14
15OUTPUT_ARCH(powerpc)
16
17PHDRS
18{
19  text PT_LOAD;
20  bss PT_LOAD;
21}
22
23SECTIONS
24{
25  /* Read-only sections, merged into text segment: */
26  . = + SIZEOF_HEADERS;
27  .interp : { *(.interp) }
28  .text      :
29  {
30    *(.text*)
31   } :text
32    _etext = .;
33    PROVIDE (etext = .);
34    .rodata    :
35   {
36    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
37  } :text
38
39  /* Read-write section, merged into data segment: */
40  . = (. + 0x00FF) & 0xFFFFFF00;
41  _erotext = .;
42  PROVIDE (erotext = .);
43  .reloc   :
44  {
45    _GOT2_TABLE_ = .;
46    KEEP(*(.got2))
47    KEEP(*(.got))
48    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
49    _FIXUP_TABLE_ = .;
50    KEEP(*(.fixup))
51  }
52  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
53  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
54
55  .data    :
56  {
57    *(.data*)
58    *(.sdata*)
59  }
60  _edata  =  .;
61  PROVIDE (edata = .);
62
63  . = .;
64
65  . = ALIGN(4);
66  .u_boot_list : {
67	KEEP(*(SORT(.u_boot_list*)));
68  }
69
70  . = .;
71  __start___ex_table = .;
72  __ex_table : { *(__ex_table) }
73  __stop___ex_table = .;
74
75  . = ALIGN(256);
76  __init_begin = .;
77  .text.init : { *(.text.init) }
78  .data.init : { *(.data.init) }
79  . = ALIGN(256);
80  __init_end = .;
81
82#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
83  .bootpg ADDR(.text) - 0x1000 :
84  {
85    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
86  } :text = 0xffff
87  . = ADDR(.text) + 0x80000;
88#else
89  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
90  {
91    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
92  } :text = 0xffff
93
94  .resetvec RESET_VECTOR_ADDRESS :
95  {
96    KEEP(*(.resetvec))
97  } :text = 0xffff
98
99  . = RESET_VECTOR_ADDRESS + 0x4;
100
101  /*
102   * Make sure that the bss segment isn't linked at 0x0, otherwise its
103   * address won't be updated during relocation fixups.  Note that
104   * this is a temporary fix.  Code to dynamically the fixup the bss
105   * location will be added in the future.  When the bss relocation
106   * fixup code is present this workaround should be removed.
107   */
108#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
109  . |= 0x10;
110#endif
111#endif
112
113  __bss_start = .;
114  .bss (NOLOAD)       :
115  {
116   *(.sbss*)
117   *(.bss*)
118   *(COMMON)
119  } :bss
120
121  . = ALIGN(4);
122  __bss_end = . ;
123  PROVIDE (end = .);
124}
125