1a47a12beSStefan Roese/* 27a577fdaSKumar Gala * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 5a47a12beSStefan Roese * project. 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 8a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 9a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 10a47a12beSStefan Roese * the License, or (at your option) any later version. 11a47a12beSStefan Roese * 12a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 13a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 14a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15a47a12beSStefan Roese * GNU General Public License for more details. 16a47a12beSStefan Roese * 17a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 18a47a12beSStefan Roese * along with this program; if not, write to the Free Software 19a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20a47a12beSStefan Roese * MA 02111-1307 USA 21a47a12beSStefan Roese */ 22a47a12beSStefan Roese 237a577fdaSKumar Gala#include "config.h" /* CONFIG_BOARDDIR */ 247a577fdaSKumar Gala 257a577fdaSKumar Gala#ifdef CONFIG_RESET_VECTOR_ADDRESS 267a577fdaSKumar Gala#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS 277a577fdaSKumar Gala#else 28a47a12beSStefan Roese#define RESET_VECTOR_ADDRESS 0xfffffffc 29a47a12beSStefan Roese#endif 30a47a12beSStefan Roese 31a47a12beSStefan RoeseOUTPUT_ARCH(powerpc) 32fbe53f59SPeter Tyser 33a47a12beSStefan RoesePHDRS 34a47a12beSStefan Roese{ 35a47a12beSStefan Roese text PT_LOAD; 36a47a12beSStefan Roese bss PT_LOAD; 37a47a12beSStefan Roese} 38a47a12beSStefan Roese 39a47a12beSStefan RoeseSECTIONS 40a47a12beSStefan Roese{ 41a47a12beSStefan Roese /* Read-only sections, merged into text segment: */ 42a47a12beSStefan Roese . = + SIZEOF_HEADERS; 43a47a12beSStefan Roese .interp : { *(.interp) } 44a47a12beSStefan Roese .text : 45a47a12beSStefan Roese { 46fbe53f59SPeter Tyser *(.text*) 47a47a12beSStefan Roese } :text 48a47a12beSStefan Roese _etext = .; 49a47a12beSStefan Roese PROVIDE (etext = .); 50a47a12beSStefan Roese .rodata : 51a47a12beSStefan Roese { 52a47a12beSStefan Roese *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 53a47a12beSStefan Roese } :text 54a47a12beSStefan Roese 55a47a12beSStefan Roese /* Read-write section, merged into data segment: */ 56a47a12beSStefan Roese . = (. + 0x00FF) & 0xFFFFFF00; 57a47a12beSStefan Roese _erotext = .; 58a47a12beSStefan Roese PROVIDE (erotext = .); 59a47a12beSStefan Roese .reloc : 60a47a12beSStefan Roese { 61a47a12beSStefan Roese _GOT2_TABLE_ = .; 62fbe53f59SPeter Tyser KEEP(*(.got2)) 63337f5f50SJoakim Tjernlund KEEP(*(.got)) 64337f5f50SJoakim Tjernlund PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); 65a47a12beSStefan Roese _FIXUP_TABLE_ = .; 66fbe53f59SPeter Tyser KEEP(*(.fixup)) 67a47a12beSStefan Roese } 68337f5f50SJoakim Tjernlund __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 69a47a12beSStefan Roese __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 70a47a12beSStefan Roese 71a47a12beSStefan Roese .data : 72a47a12beSStefan Roese { 73fbe53f59SPeter Tyser *(.data*) 74fbe53f59SPeter Tyser *(.sdata*) 75a47a12beSStefan Roese } 76a47a12beSStefan Roese _edata = .; 77a47a12beSStefan Roese PROVIDE (edata = .); 78a47a12beSStefan Roese 79a47a12beSStefan Roese . = .; 80a47a12beSStefan Roese 8155675142SMarek Vasut . = ALIGN(4); 8255675142SMarek Vasut .u_boot_list : { 83*ef123c52SAlbert ARIBAUD KEEP(*(SORT(.u_boot_list*))); 8455675142SMarek Vasut } 8555675142SMarek Vasut 86a47a12beSStefan Roese . = .; 87a47a12beSStefan Roese __start___ex_table = .; 88a47a12beSStefan Roese __ex_table : { *(__ex_table) } 89a47a12beSStefan Roese __stop___ex_table = .; 90a47a12beSStefan Roese 91a47a12beSStefan Roese . = ALIGN(256); 92a47a12beSStefan Roese __init_begin = .; 93a47a12beSStefan Roese .text.init : { *(.text.init) } 94a47a12beSStefan Roese .data.init : { *(.data.init) } 95a47a12beSStefan Roese . = ALIGN(256); 96a47a12beSStefan Roese __init_end = .; 97a47a12beSStefan Roese 98a47a12beSStefan Roese .bootpg RESET_VECTOR_ADDRESS - 0xffc : 99a47a12beSStefan Roese { 100a47a12beSStefan Roese arch/powerpc/cpu/mpc85xx/start.o (.bootpg) 101a47a12beSStefan Roese } :text = 0xffff 102a47a12beSStefan Roese 103a47a12beSStefan Roese .resetvec RESET_VECTOR_ADDRESS : 104a47a12beSStefan Roese { 105fbe53f59SPeter Tyser KEEP(*(.resetvec)) 106a47a12beSStefan Roese } :text = 0xffff 107a47a12beSStefan Roese 108a47a12beSStefan Roese . = RESET_VECTOR_ADDRESS + 0x4; 109a47a12beSStefan Roese 110a47a12beSStefan Roese /* 111a47a12beSStefan Roese * Make sure that the bss segment isn't linked at 0x0, otherwise its 112a47a12beSStefan Roese * address won't be updated during relocation fixups. Note that 113a47a12beSStefan Roese * this is a temporary fix. Code to dynamically the fixup the bss 114a47a12beSStefan Roese * location will be added in the future. When the bss relocation 115a47a12beSStefan Roese * fixup code is present this workaround should be removed. 116a47a12beSStefan Roese */ 117a47a12beSStefan Roese#if (RESET_VECTOR_ADDRESS == 0xfffffffc) 118a47a12beSStefan Roese . |= 0x10; 119a47a12beSStefan Roese#endif 120a47a12beSStefan Roese 121a47a12beSStefan Roese __bss_start = .; 122a47a12beSStefan Roese .bss (NOLOAD) : 123a47a12beSStefan Roese { 124fbe53f59SPeter Tyser *(.sbss*) 125fbe53f59SPeter Tyser *(.bss*) 126a47a12beSStefan Roese *(COMMON) 127a47a12beSStefan Roese } :bss 128a47a12beSStefan Roese 129a47a12beSStefan Roese . = ALIGN(4); 13044c6e659SPo-Yu Chuang __bss_end__ = . ; 131a47a12beSStefan Roese PROVIDE (end = .); 132a47a12beSStefan Roese} 133