1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright 2007-2009 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 5a47a12beSStefan Roese * project. 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 8a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 9a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 10a47a12beSStefan Roese * the License, or (at your option) any later version. 11a47a12beSStefan Roese * 12a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 13a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 14a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15a47a12beSStefan Roese * GNU General Public License for more details. 16a47a12beSStefan Roese * 17a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 18a47a12beSStefan Roese * along with this program; if not, write to the Free Software 19a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20a47a12beSStefan Roese * MA 02111-1307 USA 21a47a12beSStefan Roese */ 22a47a12beSStefan Roese 23a47a12beSStefan Roese#ifndef RESET_VECTOR_ADDRESS 24a47a12beSStefan Roese#define RESET_VECTOR_ADDRESS 0xfffffffc 25a47a12beSStefan Roese#endif 26a47a12beSStefan Roese 27a47a12beSStefan RoeseOUTPUT_ARCH(powerpc) 28fbe53f59SPeter Tyser 29a47a12beSStefan RoesePHDRS 30a47a12beSStefan Roese{ 31a47a12beSStefan Roese text PT_LOAD; 32a47a12beSStefan Roese bss PT_LOAD; 33a47a12beSStefan Roese} 34a47a12beSStefan Roese 35a47a12beSStefan RoeseSECTIONS 36a47a12beSStefan Roese{ 37a47a12beSStefan Roese /* Read-only sections, merged into text segment: */ 38a47a12beSStefan Roese . = + SIZEOF_HEADERS; 39a47a12beSStefan Roese .interp : { *(.interp) } 40a47a12beSStefan Roese .text : 41a47a12beSStefan Roese { 42fbe53f59SPeter Tyser *(.text*) 43a47a12beSStefan Roese } :text 44a47a12beSStefan Roese _etext = .; 45a47a12beSStefan Roese PROVIDE (etext = .); 46a47a12beSStefan Roese .rodata : 47a47a12beSStefan Roese { 48a47a12beSStefan Roese *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 49a47a12beSStefan Roese } :text 50a47a12beSStefan Roese 51a47a12beSStefan Roese /* Read-write section, merged into data segment: */ 52a47a12beSStefan Roese . = (. + 0x00FF) & 0xFFFFFF00; 53a47a12beSStefan Roese _erotext = .; 54a47a12beSStefan Roese PROVIDE (erotext = .); 55a47a12beSStefan Roese .reloc : 56a47a12beSStefan Roese { 57a47a12beSStefan Roese _GOT2_TABLE_ = .; 58fbe53f59SPeter Tyser KEEP(*(.got2)) 59*337f5f50SJoakim Tjernlund KEEP(*(.got)) 60*337f5f50SJoakim Tjernlund PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); 61a47a12beSStefan Roese _FIXUP_TABLE_ = .; 62fbe53f59SPeter Tyser KEEP(*(.fixup)) 63a47a12beSStefan Roese } 64*337f5f50SJoakim Tjernlund __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 65a47a12beSStefan Roese __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 66a47a12beSStefan Roese 67a47a12beSStefan Roese .data : 68a47a12beSStefan Roese { 69fbe53f59SPeter Tyser *(.data*) 70fbe53f59SPeter Tyser *(.sdata*) 71a47a12beSStefan Roese } 72a47a12beSStefan Roese _edata = .; 73a47a12beSStefan Roese PROVIDE (edata = .); 74a47a12beSStefan Roese 75a47a12beSStefan Roese . = .; 76a47a12beSStefan Roese __u_boot_cmd_start = .; 77a47a12beSStefan Roese .u_boot_cmd : { *(.u_boot_cmd) } 78a47a12beSStefan Roese __u_boot_cmd_end = .; 79a47a12beSStefan Roese 80a47a12beSStefan Roese . = .; 81a47a12beSStefan Roese __start___ex_table = .; 82a47a12beSStefan Roese __ex_table : { *(__ex_table) } 83a47a12beSStefan Roese __stop___ex_table = .; 84a47a12beSStefan Roese 85a47a12beSStefan Roese . = ALIGN(256); 86a47a12beSStefan Roese __init_begin = .; 87a47a12beSStefan Roese .text.init : { *(.text.init) } 88a47a12beSStefan Roese .data.init : { *(.data.init) } 89a47a12beSStefan Roese . = ALIGN(256); 90a47a12beSStefan Roese __init_end = .; 91a47a12beSStefan Roese 92a47a12beSStefan Roese .bootpg RESET_VECTOR_ADDRESS - 0xffc : 93a47a12beSStefan Roese { 94a47a12beSStefan Roese arch/powerpc/cpu/mpc85xx/start.o (.bootpg) 95a47a12beSStefan Roese } :text = 0xffff 96a47a12beSStefan Roese 97a47a12beSStefan Roese .resetvec RESET_VECTOR_ADDRESS : 98a47a12beSStefan Roese { 99fbe53f59SPeter Tyser KEEP(*(.resetvec)) 100a47a12beSStefan Roese } :text = 0xffff 101a47a12beSStefan Roese 102a47a12beSStefan Roese . = RESET_VECTOR_ADDRESS + 0x4; 103a47a12beSStefan Roese 104a47a12beSStefan Roese /* 105a47a12beSStefan Roese * Make sure that the bss segment isn't linked at 0x0, otherwise its 106a47a12beSStefan Roese * address won't be updated during relocation fixups. Note that 107a47a12beSStefan Roese * this is a temporary fix. Code to dynamically the fixup the bss 108a47a12beSStefan Roese * location will be added in the future. When the bss relocation 109a47a12beSStefan Roese * fixup code is present this workaround should be removed. 110a47a12beSStefan Roese */ 111a47a12beSStefan Roese#if (RESET_VECTOR_ADDRESS == 0xfffffffc) 112a47a12beSStefan Roese . |= 0x10; 113a47a12beSStefan Roese#endif 114a47a12beSStefan Roese 115a47a12beSStefan Roese __bss_start = .; 116a47a12beSStefan Roese .bss (NOLOAD) : 117a47a12beSStefan Roese { 118fbe53f59SPeter Tyser *(.sbss*) 119fbe53f59SPeter Tyser *(.bss*) 120a47a12beSStefan Roese *(COMMON) 121a47a12beSStefan Roese } :bss 122a47a12beSStefan Roese 123a47a12beSStefan Roese . = ALIGN(4); 124a47a12beSStefan Roese _end = . ; 125a47a12beSStefan Roese PROVIDE (end = .); 126a47a12beSStefan Roese} 127