1a47a12beSStefan Roese/* 27a577fdaSKumar Gala * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 77a577fdaSKumar Gala#include "config.h" /* CONFIG_BOARDDIR */ 87a577fdaSKumar Gala 97a577fdaSKumar Gala#ifdef CONFIG_RESET_VECTOR_ADDRESS 107a577fdaSKumar Gala#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS 117a577fdaSKumar Gala#else 12a47a12beSStefan Roese#define RESET_VECTOR_ADDRESS 0xfffffffc 13a47a12beSStefan Roese#endif 14a47a12beSStefan Roese 15a47a12beSStefan RoeseOUTPUT_ARCH(powerpc) 16fbe53f59SPeter Tyser 17a47a12beSStefan RoesePHDRS 18a47a12beSStefan Roese{ 19a47a12beSStefan Roese text PT_LOAD; 20a47a12beSStefan Roese bss PT_LOAD; 21a47a12beSStefan Roese} 22a47a12beSStefan Roese 23a47a12beSStefan RoeseSECTIONS 24a47a12beSStefan Roese{ 25a47a12beSStefan Roese /* Read-only sections, merged into text segment: */ 26a47a12beSStefan Roese . = + SIZEOF_HEADERS; 27a47a12beSStefan Roese .interp : { *(.interp) } 28a47a12beSStefan Roese .text : 29a47a12beSStefan Roese { 30fbe53f59SPeter Tyser *(.text*) 31a47a12beSStefan Roese } :text 32a47a12beSStefan Roese _etext = .; 33a47a12beSStefan Roese PROVIDE (etext = .); 34a47a12beSStefan Roese .rodata : 35a47a12beSStefan Roese { 36a47a12beSStefan Roese *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 37a47a12beSStefan Roese } :text 38a47a12beSStefan Roese 39a47a12beSStefan Roese /* Read-write section, merged into data segment: */ 40a47a12beSStefan Roese . = (. + 0x00FF) & 0xFFFFFF00; 41a47a12beSStefan Roese _erotext = .; 42a47a12beSStefan Roese PROVIDE (erotext = .); 43a47a12beSStefan Roese .reloc : 44a47a12beSStefan Roese { 45a47a12beSStefan Roese _GOT2_TABLE_ = .; 46fbe53f59SPeter Tyser KEEP(*(.got2)) 47337f5f50SJoakim Tjernlund KEEP(*(.got)) 48337f5f50SJoakim Tjernlund PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); 49a47a12beSStefan Roese _FIXUP_TABLE_ = .; 50fbe53f59SPeter Tyser KEEP(*(.fixup)) 51a47a12beSStefan Roese } 52337f5f50SJoakim Tjernlund __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 53a47a12beSStefan Roese __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 54a47a12beSStefan Roese 55a47a12beSStefan Roese .data : 56a47a12beSStefan Roese { 57fbe53f59SPeter Tyser *(.data*) 58fbe53f59SPeter Tyser *(.sdata*) 59a47a12beSStefan Roese } 60a47a12beSStefan Roese _edata = .; 61a47a12beSStefan Roese PROVIDE (edata = .); 62a47a12beSStefan Roese 63a47a12beSStefan Roese . = .; 64a47a12beSStefan Roese 6555675142SMarek Vasut . = ALIGN(4); 6655675142SMarek Vasut .u_boot_list : { 67ef123c52SAlbert ARIBAUD KEEP(*(SORT(.u_boot_list*))); 6855675142SMarek Vasut } 6955675142SMarek Vasut 70a47a12beSStefan Roese . = .; 71a47a12beSStefan Roese __start___ex_table = .; 72a47a12beSStefan Roese __ex_table : { *(__ex_table) } 73a47a12beSStefan Roese __stop___ex_table = .; 74a47a12beSStefan Roese 75a47a12beSStefan Roese . = ALIGN(256); 76a47a12beSStefan Roese __init_begin = .; 77a47a12beSStefan Roese .text.init : { *(.text.init) } 78a47a12beSStefan Roese .data.init : { *(.data.init) } 79a47a12beSStefan Roese . = ALIGN(256); 80a47a12beSStefan Roese __init_end = .; 81a47a12beSStefan Roese 825df572f0SYing Zhang#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC 835df572f0SYing Zhang .bootpg ADDR(.text) - 0x1000 : 845df572f0SYing Zhang { 855df572f0SYing Zhang KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) 865df572f0SYing Zhang } :text = 0xffff 875df572f0SYing Zhang . = ADDR(.text) + 0x80000; 885df572f0SYing Zhang#else 89a47a12beSStefan Roese .bootpg RESET_VECTOR_ADDRESS - 0xffc : 90a47a12beSStefan Roese { 91a47a12beSStefan Roese arch/powerpc/cpu/mpc85xx/start.o (.bootpg) 92a47a12beSStefan Roese } :text = 0xffff 93a47a12beSStefan Roese 94a47a12beSStefan Roese .resetvec RESET_VECTOR_ADDRESS : 95a47a12beSStefan Roese { 96fbe53f59SPeter Tyser KEEP(*(.resetvec)) 97a47a12beSStefan Roese } :text = 0xffff 98a47a12beSStefan Roese 99a47a12beSStefan Roese . = RESET_VECTOR_ADDRESS + 0x4; 100a47a12beSStefan Roese 101a47a12beSStefan Roese /* 102a47a12beSStefan Roese * Make sure that the bss segment isn't linked at 0x0, otherwise its 103a47a12beSStefan Roese * address won't be updated during relocation fixups. Note that 104a47a12beSStefan Roese * this is a temporary fix. Code to dynamically the fixup the bss 105a47a12beSStefan Roese * location will be added in the future. When the bss relocation 106a47a12beSStefan Roese * fixup code is present this workaround should be removed. 107a47a12beSStefan Roese */ 108a47a12beSStefan Roese#if (RESET_VECTOR_ADDRESS == 0xfffffffc) 109a47a12beSStefan Roese . |= 0x10; 110a47a12beSStefan Roese#endif 1115df572f0SYing Zhang#endif 112a47a12beSStefan Roese 113a47a12beSStefan Roese __bss_start = .; 114a47a12beSStefan Roese .bss (NOLOAD) : 115a47a12beSStefan Roese { 116fbe53f59SPeter Tyser *(.sbss*) 117fbe53f59SPeter Tyser *(.bss*) 118a47a12beSStefan Roese *(COMMON) 119a47a12beSStefan Roese } :bss 120a47a12beSStefan Roese 121a47a12beSStefan Roese . = ALIGN(4); 1223929fb0aSSimon Glass __bss_end = . ; 123a47a12beSStefan Roese PROVIDE (end = .); 124a47a12beSStefan Roese} 125