1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #ifdef CONFIG_ADDR_MAP 30 #include <addr_map.h> 31 #endif 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 void invalidate_tlb(u8 tlb) 36 { 37 if (tlb == 0) 38 mtspr(MMUCSR0, 0x4); 39 if (tlb == 1) 40 mtspr(MMUCSR0, 0x2); 41 } 42 43 void init_tlbs(void) 44 { 45 int i; 46 47 for (i = 0; i < num_tlb_entries; i++) { 48 write_tlb(tlb_table[i].mas0, 49 tlb_table[i].mas1, 50 tlb_table[i].mas2, 51 tlb_table[i].mas3, 52 tlb_table[i].mas7); 53 } 54 55 return ; 56 } 57 58 #ifndef CONFIG_NAND_SPL 59 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 60 phys_addr_t *rpn) 61 { 62 u32 _mas1; 63 64 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); 65 asm volatile("tlbre;isync"); 66 _mas1 = mfspr(MAS1); 67 68 *valid = (_mas1 & MAS1_VALID); 69 *tsize = (_mas1 >> 8) & 0xf; 70 *epn = mfspr(MAS2) & MAS2_EPN; 71 *rpn = mfspr(MAS3) & MAS3_RPN; 72 #ifdef CONFIG_ENABLE_36BIT_PHYS 73 *rpn |= ((u64)mfspr(MAS7)) << 32; 74 #endif 75 } 76 77 void print_tlbcam(void) 78 { 79 int i; 80 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 81 82 /* walk all the entries */ 83 printf("TLBCAM entries\n"); 84 for (i = 0; i < num_cam; i++) { 85 unsigned long epn; 86 u32 tsize, valid; 87 phys_addr_t rpn; 88 89 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); 90 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", 91 i, (valid == 0) ? 0 : 1, (unsigned int)epn, 92 (unsigned long long)rpn); 93 print_size(TSIZE_TO_BYTES(tsize), "\n"); 94 } 95 } 96 97 static inline void use_tlb_cam(u8 idx) 98 { 99 int i = idx / 32; 100 int bit = idx % 32; 101 102 gd->used_tlb_cams[i] |= (1 << bit); 103 } 104 105 static inline void free_tlb_cam(u8 idx) 106 { 107 int i = idx / 32; 108 int bit = idx % 32; 109 110 gd->used_tlb_cams[i] &= ~(1 << bit); 111 } 112 113 void init_used_tlb_cams(void) 114 { 115 int i; 116 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 117 118 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) 119 gd->used_tlb_cams[i] = 0; 120 121 /* walk all the entries */ 122 for (i = 0; i < num_cam; i++) { 123 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); 124 asm volatile("tlbre;isync"); 125 if (mfspr(MAS1) & MAS1_VALID) 126 use_tlb_cam(i); 127 } 128 } 129 130 int find_free_tlbcam(void) 131 { 132 int i; 133 u32 idx; 134 135 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { 136 idx = ffz(gd->used_tlb_cams[i]); 137 138 if (idx != 32) 139 break; 140 } 141 142 idx += i * 32; 143 144 if (idx >= CONFIG_SYS_NUM_TLBCAMS) 145 return -1; 146 147 return idx; 148 } 149 150 void set_tlb(u8 tlb, u32 epn, u64 rpn, 151 u8 perms, u8 wimge, 152 u8 ts, u8 esel, u8 tsize, u8 iprot) 153 { 154 u32 _mas0, _mas1, _mas2, _mas3, _mas7; 155 156 if (tlb == 1) 157 use_tlb_cam(esel); 158 159 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); 160 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); 161 _mas2 = FSL_BOOKE_MAS2(epn, wimge); 162 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); 163 _mas7 = FSL_BOOKE_MAS7(rpn); 164 165 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); 166 167 #ifdef CONFIG_ADDR_MAP 168 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) 169 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); 170 #endif 171 } 172 173 void disable_tlb(u8 esel) 174 { 175 u32 _mas0, _mas1, _mas2, _mas3, _mas7; 176 177 free_tlb_cam(esel); 178 179 _mas0 = FSL_BOOKE_MAS0(1, esel, 0); 180 _mas1 = 0; 181 _mas2 = 0; 182 _mas3 = 0; 183 _mas7 = 0; 184 185 mtspr(MAS0, _mas0); 186 mtspr(MAS1, _mas1); 187 mtspr(MAS2, _mas2); 188 mtspr(MAS3, _mas3); 189 #ifdef CONFIG_ENABLE_36BIT_PHYS 190 mtspr(MAS7, _mas7); 191 #endif 192 asm volatile("isync;msync;tlbwe;isync"); 193 194 #ifdef CONFIG_ADDR_MAP 195 if (gd->flags & GD_FLG_RELOC) 196 addrmap_set_entry(0, 0, 0, esel); 197 #endif 198 } 199 200 static void tlbsx (const volatile unsigned *addr) 201 { 202 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); 203 } 204 205 /* return -1 if we didn't find anything */ 206 int find_tlb_idx(void *addr, u8 tlbsel) 207 { 208 u32 _mas0, _mas1; 209 210 /* zero out Search PID, AS */ 211 mtspr(MAS6, 0); 212 213 tlbsx(addr); 214 215 _mas0 = mfspr(MAS0); 216 _mas1 = mfspr(MAS1); 217 218 /* we found something, and its in the TLB we expect */ 219 if ((MAS1_VALID & _mas1) && 220 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { 221 return ((_mas0 & MAS0_ESEL_MSK) >> 16); 222 } 223 224 return -1; 225 } 226 227 #ifdef CONFIG_ADDR_MAP 228 void init_addr_map(void) 229 { 230 int i; 231 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 232 233 /* walk all the entries */ 234 for (i = 0; i < num_cam; i++) { 235 unsigned long epn; 236 u32 tsize, valid; 237 phys_addr_t rpn; 238 239 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); 240 if (valid & MAS1_VALID) 241 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); 242 } 243 244 return ; 245 } 246 #endif 247 248 unsigned int 249 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) 250 { 251 int i; 252 unsigned int tlb_size; 253 unsigned int wimge = 0; 254 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; 255 unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; 256 u64 size, memsize = (u64)memsize_in_meg << 20; 257 258 #ifdef CONFIG_SYS_PPC_DDR_WIMGE 259 wimge = CONFIG_SYS_PPC_DDR_WIMGE; 260 #endif 261 size = min(memsize, CONFIG_MAX_MEM_MAPPED); 262 263 /* Convert (4^max) kB to (2^max) bytes */ 264 max_cam = max_cam * 2 + 10; 265 266 for (i = 0; size && i < 8; i++) { 267 int ram_tlb_index = find_free_tlbcam(); 268 u32 camsize = __ilog2_u64(size) & ~1U; 269 u32 align = __ilog2(ram_tlb_address) & ~1U; 270 271 if (ram_tlb_index == -1) 272 break; 273 274 if (align == -2) align = max_cam; 275 if (camsize > align) 276 camsize = align; 277 278 if (camsize > max_cam) 279 camsize = max_cam; 280 281 tlb_size = (camsize - 10) / 2; 282 283 set_tlb(1, ram_tlb_address, p_addr, 284 MAS3_SX|MAS3_SW|MAS3_SR, wimge, 285 0, ram_tlb_index, tlb_size, 1); 286 287 size -= 1ULL << camsize; 288 memsize -= 1ULL << camsize; 289 ram_tlb_address += 1UL << camsize; 290 p_addr += 1UL << camsize; 291 } 292 293 if (memsize) 294 print_size(memsize, " left unmapped\n"); 295 return memsize_in_meg; 296 } 297 298 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) 299 { 300 return 301 setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); 302 } 303 304 /* Invalidate the DDR TLBs for the requested size */ 305 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) 306 { 307 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 308 unsigned long epn; 309 u32 tsize, valid, ptr; 310 phys_addr_t rpn = 0; 311 int ddr_esel; 312 u64 memsize = (u64)memsize_in_meg << 20; 313 314 ptr = vstart; 315 316 while (ptr < (vstart + memsize)) { 317 ddr_esel = find_tlb_idx((void *)ptr, 1); 318 if (ddr_esel != -1) { 319 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 320 disable_tlb(ddr_esel); 321 } 322 ptr += TSIZE_TO_BYTES(tsize); 323 } 324 } 325 326 void clear_ddr_tlbs(unsigned int memsize_in_meg) 327 { 328 clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); 329 } 330 331 332 #endif /* !CONFIG_NAND_SPL */ 333