1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/processor.h> 12 #include <asm/mmu.h> 13 #ifdef CONFIG_ADDR_MAP 14 #include <addr_map.h> 15 #endif 16 17 #include <linux/log2.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 void invalidate_tlb(u8 tlb) 22 { 23 if (tlb == 0) 24 mtspr(MMUCSR0, 0x4); 25 if (tlb == 1) 26 mtspr(MMUCSR0, 0x2); 27 } 28 29 __weak void init_tlbs(void) 30 { 31 int i; 32 33 for (i = 0; i < num_tlb_entries; i++) { 34 write_tlb(tlb_table[i].mas0, 35 tlb_table[i].mas1, 36 tlb_table[i].mas2, 37 tlb_table[i].mas3, 38 tlb_table[i].mas7); 39 } 40 41 return ; 42 } 43 44 #if !defined(CONFIG_NAND_SPL) && \ 45 (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) 46 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 47 phys_addr_t *rpn) 48 { 49 u32 _mas1; 50 51 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); 52 asm volatile("tlbre;isync"); 53 _mas1 = mfspr(MAS1); 54 55 *valid = (_mas1 & MAS1_VALID); 56 *tsize = (_mas1 >> 7) & 0x1f; 57 *epn = mfspr(MAS2) & MAS2_EPN; 58 *rpn = mfspr(MAS3) & MAS3_RPN; 59 #ifdef CONFIG_ENABLE_36BIT_PHYS 60 *rpn |= ((u64)mfspr(MAS7)) << 32; 61 #endif 62 } 63 64 void print_tlbcam(void) 65 { 66 int i; 67 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 68 69 /* walk all the entries */ 70 printf("TLBCAM entries\n"); 71 for (i = 0; i < num_cam; i++) { 72 unsigned long epn; 73 u32 tsize, valid; 74 phys_addr_t rpn; 75 76 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); 77 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", 78 i, (valid == 0) ? 0 : 1, (unsigned int)epn, 79 (unsigned long long)rpn); 80 print_size(TSIZE_TO_BYTES(tsize), "\n"); 81 } 82 } 83 84 static inline void use_tlb_cam(u8 idx) 85 { 86 int i = idx / 32; 87 int bit = idx % 32; 88 89 gd->arch.used_tlb_cams[i] |= (1 << bit); 90 } 91 92 static inline void free_tlb_cam(u8 idx) 93 { 94 int i = idx / 32; 95 int bit = idx % 32; 96 97 gd->arch.used_tlb_cams[i] &= ~(1 << bit); 98 } 99 100 void init_used_tlb_cams(void) 101 { 102 int i; 103 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 104 105 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) 106 gd->arch.used_tlb_cams[i] = 0; 107 108 /* walk all the entries */ 109 for (i = 0; i < num_cam; i++) { 110 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); 111 asm volatile("tlbre;isync"); 112 if (mfspr(MAS1) & MAS1_VALID) 113 use_tlb_cam(i); 114 } 115 } 116 117 int find_free_tlbcam(void) 118 { 119 int i; 120 u32 idx; 121 122 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { 123 idx = ffz(gd->arch.used_tlb_cams[i]); 124 125 if (idx != 32) 126 break; 127 } 128 129 idx += i * 32; 130 131 if (idx >= CONFIG_SYS_NUM_TLBCAMS) 132 return -1; 133 134 return idx; 135 } 136 137 void set_tlb(u8 tlb, u32 epn, u64 rpn, 138 u8 perms, u8 wimge, 139 u8 ts, u8 esel, u8 tsize, u8 iprot) 140 { 141 u32 _mas0, _mas1, _mas2, _mas3, _mas7; 142 143 if (tlb == 1) 144 use_tlb_cam(esel); 145 146 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && 147 tsize & 1) { 148 printf("%s: bad tsize %d on entry %d at 0x%08x\n", 149 __func__, tsize, tlb, epn); 150 return; 151 } 152 153 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); 154 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); 155 _mas2 = FSL_BOOKE_MAS2(epn, wimge); 156 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); 157 _mas7 = FSL_BOOKE_MAS7(rpn); 158 159 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); 160 161 #ifdef CONFIG_ADDR_MAP 162 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) 163 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); 164 #endif 165 } 166 167 void disable_tlb(u8 esel) 168 { 169 u32 _mas0, _mas1, _mas2, _mas3; 170 171 free_tlb_cam(esel); 172 173 _mas0 = FSL_BOOKE_MAS0(1, esel, 0); 174 _mas1 = 0; 175 _mas2 = 0; 176 _mas3 = 0; 177 178 mtspr(MAS0, _mas0); 179 mtspr(MAS1, _mas1); 180 mtspr(MAS2, _mas2); 181 mtspr(MAS3, _mas3); 182 #ifdef CONFIG_ENABLE_36BIT_PHYS 183 mtspr(MAS7, 0); 184 #endif 185 asm volatile("isync;msync;tlbwe;isync"); 186 187 #ifdef CONFIG_ADDR_MAP 188 if (gd->flags & GD_FLG_RELOC) 189 addrmap_set_entry(0, 0, 0, esel); 190 #endif 191 } 192 193 static void tlbsx (const volatile unsigned *addr) 194 { 195 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); 196 } 197 198 /* return -1 if we didn't find anything */ 199 int find_tlb_idx(void *addr, u8 tlbsel) 200 { 201 u32 _mas0, _mas1; 202 203 /* zero out Search PID, AS */ 204 mtspr(MAS6, 0); 205 206 tlbsx(addr); 207 208 _mas0 = mfspr(MAS0); 209 _mas1 = mfspr(MAS1); 210 211 /* we found something, and its in the TLB we expect */ 212 if ((MAS1_VALID & _mas1) && 213 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { 214 return ((_mas0 & MAS0_ESEL_MSK) >> 16); 215 } 216 217 return -1; 218 } 219 220 #ifdef CONFIG_ADDR_MAP 221 void init_addr_map(void) 222 { 223 int i; 224 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; 225 226 /* walk all the entries */ 227 for (i = 0; i < num_cam; i++) { 228 unsigned long epn; 229 u32 tsize, valid; 230 phys_addr_t rpn; 231 232 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); 233 if (valid & MAS1_VALID) 234 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); 235 } 236 237 return ; 238 } 239 #endif 240 241 uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, 242 enum tlb_map_type map_type) 243 { 244 int i; 245 unsigned int tlb_size; 246 unsigned int wimge; 247 unsigned int perm; 248 unsigned int max_cam, tsize_mask; 249 250 if (map_type == TLB_MAP_RAM) { 251 perm = MAS3_SX|MAS3_SW|MAS3_SR; 252 wimge = MAS2_M; 253 #ifdef CONFIG_SYS_PPC_DDR_WIMGE 254 wimge = CONFIG_SYS_PPC_DDR_WIMGE; 255 #endif 256 } else { 257 perm = MAS3_SW|MAS3_SR; 258 wimge = MAS2_I|MAS2_G; 259 } 260 261 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { 262 /* Convert (4^max) kB to (2^max) bytes */ 263 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; 264 tsize_mask = ~1U; 265 } else { 266 /* Convert (2^max) kB to (2^max) bytes */ 267 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10; 268 tsize_mask = ~0U; 269 } 270 271 for (i = 0; size && i < 8; i++) { 272 int tlb_index = find_free_tlbcam(); 273 u32 camsize = __ilog2_u64(size) & tsize_mask; 274 u32 align = __ilog2(v_addr) & tsize_mask; 275 276 if (tlb_index == -1) 277 break; 278 279 if (align == -2) align = max_cam; 280 if (camsize > align) 281 camsize = align; 282 283 if (camsize > max_cam) 284 camsize = max_cam; 285 286 tlb_size = camsize - 10; 287 288 set_tlb(1, v_addr, p_addr, perm, wimge, 289 0, tlb_index, tlb_size, 1); 290 291 size -= 1ULL << camsize; 292 v_addr += 1UL << camsize; 293 p_addr += 1UL << camsize; 294 } 295 296 return size; 297 } 298 299 unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, 300 unsigned int memsize_in_meg) 301 { 302 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; 303 u64 memsize = (u64)memsize_in_meg << 20; 304 u64 size; 305 306 size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); 307 size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); 308 309 if (size || memsize > CONFIG_MAX_MEM_MAPPED) { 310 print_size(memsize > CONFIG_MAX_MEM_MAPPED ? 311 memsize - CONFIG_MAX_MEM_MAPPED + size : size, 312 " left unmapped\n"); 313 } 314 315 return memsize_in_meg; 316 } 317 318 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) 319 { 320 return 321 setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); 322 } 323 324 /* Invalidate the DDR TLBs for the requested size */ 325 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) 326 { 327 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 328 unsigned long epn; 329 u32 tsize, valid, ptr; 330 phys_addr_t rpn = 0; 331 int ddr_esel; 332 u64 memsize = (u64)memsize_in_meg << 20; 333 334 ptr = vstart; 335 336 while (ptr < (vstart + memsize)) { 337 ddr_esel = find_tlb_idx((void *)ptr, 1); 338 if (ddr_esel != -1) { 339 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 340 disable_tlb(ddr_esel); 341 } 342 ptr += TSIZE_TO_BYTES(tsize); 343 } 344 } 345 346 void clear_ddr_tlbs(unsigned int memsize_in_meg) 347 { 348 clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); 349 } 350 351 352 #endif /* not SPL */ 353