1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet2_serdes.h" 28 29 struct serdes_config { 30 u32 protocol; 31 u8 lanes[SRDS_MAX_LANES]; 32 }; 33 34 static struct serdes_config serdes1_cfg_tbl[] = { 35 /* SerDes 1 */ 36 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 37 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 38 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 39 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 40 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 41 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 42 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 43 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, 44 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 45 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 46 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 47 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, 48 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 49 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 50 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 51 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, 52 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 53 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 54 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 55 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, 56 {38, {NONE, NONE, QSGMII_FM1_B, NONE, 57 NONE, NONE, QSGMII_FM1_A, NONE}}, 58 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 59 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 60 NONE, NONE, QSGMII_FM1_A, NONE}}, 61 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 62 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 63 NONE, NONE, QSGMII_FM1_A, NONE}}, 64 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 65 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 66 NONE, NONE, QSGMII_FM1_A, NONE}}, 67 {} 68 }; 69 static struct serdes_config serdes2_cfg_tbl[] = { 70 /* SerDes 2 */ 71 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 72 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 73 XAUI_FM2_MAC10, XAUI_FM2_MAC10, 74 XAUI_FM2_MAC10, XAUI_FM2_MAC10}}, 75 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 76 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 77 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, 78 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, 79 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 80 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, 82 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, 83 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 84 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 85 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 86 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 87 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 88 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 89 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 90 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 91 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 92 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 93 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 94 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 95 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 96 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 97 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 98 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 99 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 100 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 101 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 102 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 103 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 104 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 105 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 106 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 107 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 108 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 109 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 110 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 111 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 112 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 113 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 114 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 115 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 116 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 117 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 118 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 119 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 120 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 121 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 122 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 123 {38, {NONE, NONE, QSGMII_FM2_B, NONE, 124 NONE, NONE, QSGMII_FM1_A, NONE}}, 125 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 126 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 127 NONE, NONE, QSGMII_FM1_A, NONE}}, 128 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 129 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 130 NONE, NONE, QSGMII_FM1_A, NONE}}, 131 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 132 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 133 NONE, NONE, QSGMII_FM1_A, NONE}}, 134 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 135 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 136 NONE, NONE, QSGMII_FM1_A, NONE}}, 137 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 138 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 139 NONE, NONE, QSGMII_FM1_A, NONE}}, 140 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 141 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 142 NONE, NONE, QSGMII_FM1_A, NONE}}, 143 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, 144 XFI_FM2_MAC10, XFI_FM2_MAC9, 145 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 146 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 147 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10, 148 XFI_FM2_MAC10, XFI_FM2_MAC9, 149 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 150 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 151 {} 152 }; 153 static struct serdes_config serdes3_cfg_tbl[] = { 154 /* SerDes 3 */ 155 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, 156 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, 157 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, 158 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, 159 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 160 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, 161 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 162 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, 163 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 164 PCIE2, PCIE2, PCIE2, PCIE2}}, 165 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 166 PCIE2, PCIE2, PCIE2, PCIE2}}, 167 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 168 SRIO1, SRIO1, SRIO1, SRIO1}}, 169 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 170 SRIO1, SRIO1, SRIO1, SRIO1}}, 171 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 172 SRIO1, SRIO1, SRIO1, SRIO1}}, 173 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 174 SRIO1, SRIO1, SRIO1, SRIO1}}, 175 {} 176 }; 177 static struct serdes_config serdes4_cfg_tbl[] = { 178 /* SerDes 4 */ 179 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, 180 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, 181 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, 182 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, 183 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}}, 184 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}}, 185 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, 186 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, 187 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, 188 {} 189 }; 190 static struct serdes_config *serdes_cfg_tbl[] = { 191 serdes1_cfg_tbl, 192 serdes2_cfg_tbl, 193 serdes3_cfg_tbl, 194 serdes4_cfg_tbl, 195 }; 196 197 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 198 { 199 struct serdes_config *ptr; 200 201 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 202 return 0; 203 204 ptr = serdes_cfg_tbl[serdes]; 205 while (ptr->protocol) { 206 if (ptr->protocol == cfg) 207 return ptr->lanes[lane]; 208 ptr++; 209 } 210 return 0; 211 } 212 213 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 214 { 215 int i; 216 struct serdes_config *ptr; 217 218 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 219 return 0; 220 221 ptr = serdes_cfg_tbl[serdes]; 222 while (ptr->protocol) { 223 if (ptr->protocol == prtcl) 224 break; 225 ptr++; 226 } 227 228 if (!ptr->protocol) 229 return 0; 230 231 for (i = 0; i < SRDS_MAX_LANES; i++) { 232 if (ptr->lanes[i] != NONE) 233 return 1; 234 } 235 236 return 0; 237 } 238