1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include "fsl_corenet2_serdes.h" 12 13 struct serdes_config { 14 u32 protocol; 15 u8 lanes[SRDS_MAX_LANES]; 16 }; 17 18 #ifdef CONFIG_PPC_T4240 19 static const struct serdes_config serdes1_cfg_tbl[] = { 20 /* SerDes 1 */ 21 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 22 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 23 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 24 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 25 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 26 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 28 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, 29 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 30 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 32 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, 33 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 34 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, 37 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 38 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 39 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 40 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, 41 {38, {NONE, NONE, QSGMII_FM1_B, NONE, 42 NONE, NONE, QSGMII_FM1_A, NONE}}, 43 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 44 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 45 NONE, NONE, QSGMII_FM1_A, NONE}}, 46 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 47 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 48 NONE, NONE, QSGMII_FM1_A, NONE}}, 49 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 50 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 51 NONE, NONE, QSGMII_FM1_A, NONE}}, 52 {} 53 }; 54 static const struct serdes_config serdes2_cfg_tbl[] = { 55 /* SerDes 2 */ 56 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 57 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 58 XAUI_FM2_MAC10, XAUI_FM2_MAC10, 59 XAUI_FM2_MAC10, XAUI_FM2_MAC10}}, 60 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 61 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 62 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, 63 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, 64 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 65 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 66 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, 67 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, 68 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 69 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 70 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 71 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 72 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 73 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 74 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 75 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 76 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 77 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 78 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 79 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 80 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 81 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 82 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 83 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 84 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 85 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 86 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 87 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 88 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 89 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 90 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 91 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 92 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 93 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 94 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 95 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 96 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 97 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 98 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 99 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 100 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 101 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 102 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 103 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 104 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 105 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 106 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 107 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 108 {38, {NONE, NONE, QSGMII_FM2_B, NONE, 109 NONE, NONE, QSGMII_FM2_A, NONE} }, 110 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 111 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 112 NONE, NONE, QSGMII_FM2_A, NONE} }, 113 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 114 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 115 NONE, NONE, QSGMII_FM2_A, NONE} }, 116 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 117 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 118 NONE, NONE, QSGMII_FM2_A, NONE} }, 119 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 120 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 121 NONE, NONE, QSGMII_FM2_A, NONE} }, 122 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 123 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 124 NONE, NONE, QSGMII_FM2_A, NONE} }, 125 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 126 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 127 NONE, NONE, QSGMII_FM2_A, NONE} }, 128 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, 129 XFI_FM2_MAC10, XFI_FM2_MAC9, 130 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 131 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 132 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10, 133 XFI_FM2_MAC10, XFI_FM2_MAC9, 134 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 135 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, 136 {} 137 }; 138 static const struct serdes_config serdes3_cfg_tbl[] = { 139 /* SerDes 3 */ 140 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, 141 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, 142 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, 143 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, 144 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 145 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, 146 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 147 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, 148 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 149 PCIE2, PCIE2, PCIE2, PCIE2}}, 150 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 151 PCIE2, PCIE2, PCIE2, PCIE2}}, 152 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 153 SRIO1, SRIO1, SRIO1, SRIO1}}, 154 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 155 SRIO1, SRIO1, SRIO1, SRIO1}}, 156 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 157 SRIO1, SRIO1, SRIO1, SRIO1}}, 158 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 159 SRIO1, SRIO1, SRIO1, SRIO1}}, 160 {} 161 }; 162 static const struct serdes_config serdes4_cfg_tbl[] = { 163 /* SerDes 4 */ 164 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, 165 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, 166 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, 167 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, 168 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, 169 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, 170 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, 171 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, 172 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, 173 {} 174 }; 175 #elif defined(CONFIG_PPC_T4160) 176 static const struct serdes_config serdes1_cfg_tbl[] = { 177 /* SerDes 1 */ 178 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 179 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 180 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 181 XAUI_FM1_MAC10, XAUI_FM1_MAC10} }, 182 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 183 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 184 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 185 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, 186 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 187 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 188 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, 189 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, 190 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 191 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 192 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 193 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, 194 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 195 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, 196 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 197 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, 198 {38, {NONE, NONE, QSGMII_FM1_B, NONE, 199 NONE, NONE, QSGMII_FM1_A, NONE} }, 200 {} 201 }; 202 static const struct serdes_config serdes2_cfg_tbl[] = { 203 /* SerDes 2 */ 204 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 205 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 206 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 207 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 208 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 209 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 210 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 211 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 212 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 213 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 214 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 215 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 216 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 217 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 218 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 219 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 220 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 221 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 222 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 223 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 224 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 225 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 226 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 227 NONE, NONE} }, 228 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 229 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 230 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 231 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 232 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 233 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 234 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 235 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 236 {38, {NONE, NONE, QSGMII_FM2_B, NONE, 237 NONE, QSGMII_FM1_A, NONE, NONE} }, 238 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 239 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 240 NONE, QSGMII_FM1_A, NONE, NONE} }, 241 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 242 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 243 NONE, QSGMII_FM1_A, NONE, NONE} }, 244 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, 245 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, 246 NONE, QSGMII_FM1_A, NONE, NONE} }, 247 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, 248 XAUI_FM2_MAC9, XAUI_FM2_MAC9, 249 NONE, NONE, NONE, NONE} }, 250 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 251 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 252 NONE, NONE, NONE, NONE} }, 253 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 254 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, 255 NONE, NONE, NONE, NONE} }, 256 {56, {NONE, XFI_FM1_MAC10, 257 XFI_FM2_MAC10, NONE, 258 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 259 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, 260 {57, {NONE, XFI_FM1_MAC10, 261 XFI_FM2_MAC10, NONE, 262 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 263 NONE, NONE} }, 264 {} 265 }; 266 static const struct serdes_config serdes3_cfg_tbl[] = { 267 /* SerDes 3 */ 268 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 269 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, 270 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, 271 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, 272 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 273 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, 274 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 275 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, 276 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 277 PCIE2, PCIE2, PCIE2, PCIE2} }, 278 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 279 PCIE2, PCIE2, PCIE2, PCIE2} }, 280 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 281 SRIO1, SRIO1, SRIO1, SRIO1} }, 282 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 283 SRIO1, SRIO1, SRIO1, SRIO1} }, 284 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 285 SRIO1, SRIO1, SRIO1, SRIO1} }, 286 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, 287 NONE, NONE, NONE, NONE} }, 288 {} 289 }; 290 static const struct serdes_config serdes4_cfg_tbl[] = { 291 /* SerDes 4 */ 292 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, 293 {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, 294 {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, 295 {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, 296 {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, 297 {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, 298 {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, 299 {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, 300 {} 301 } 302 ; 303 #else 304 #error "Need to define SerDes protocol" 305 #endif 306 static const struct serdes_config *serdes_cfg_tbl[] = { 307 serdes1_cfg_tbl, 308 serdes2_cfg_tbl, 309 serdes3_cfg_tbl, 310 serdes4_cfg_tbl, 311 }; 312 313 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 314 { 315 const struct serdes_config *ptr; 316 317 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 318 return 0; 319 320 ptr = serdes_cfg_tbl[serdes]; 321 while (ptr->protocol) { 322 if (ptr->protocol == cfg) 323 return ptr->lanes[lane]; 324 ptr++; 325 } 326 return 0; 327 } 328 329 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 330 { 331 int i; 332 const struct serdes_config *ptr; 333 334 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 335 return 0; 336 337 ptr = serdes_cfg_tbl[serdes]; 338 while (ptr->protocol) { 339 if (ptr->protocol == prtcl) 340 break; 341 ptr++; 342 } 343 344 if (!ptr->protocol) 345 return 0; 346 347 for (i = 0; i < SRDS_MAX_LANES; i++) { 348 if (ptr->lanes[i] != NONE) 349 return 1; 350 } 351 352 return 0; 353 } 354