1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/fsl_serdes.h> 11 #include <asm/processor.h> 12 #include "fsl_corenet2_serdes.h" 13 14 struct serdes_config { 15 u32 protocol; 16 u8 lanes[SRDS_MAX_LANES]; 17 }; 18 19 static const struct serdes_config serdes1_cfg_tbl[] = { 20 /* SerDes 1 */ 21 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, 22 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 23 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 24 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, 25 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, 26 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 27 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 28 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 29 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 30 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 31 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 32 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, 33 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 34 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, 35 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 36 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 37 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 38 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 39 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 40 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 41 SGMII_FM1_DTSEC2, PCIE4, PCIE1, 42 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 43 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, 44 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 45 PCIE4, PCIE4, PCIE4, PCIE4} }, 46 #if defined(CONFIG_PPC_T2080) 47 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 48 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 49 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 50 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 51 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 52 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 53 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 54 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 55 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 56 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 58 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 59 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 60 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 61 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 62 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 63 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 64 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 65 PCIE4, SGMII_FM1_DTSEC4, 66 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 67 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 68 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 69 PCIE4, SGMII_FM1_DTSEC4, 70 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 71 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 72 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 73 PCIE4, SGMII_FM1_DTSEC4, 74 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 75 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, 76 XFI_FM1_MAC1, XFI_FM1_MAC2, 77 PCIE4, SGMII_FM1_DTSEC4, 78 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 79 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, 80 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 81 PCIE4, PCIE4, PCIE4, PCIE4} }, 82 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, 83 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 84 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 85 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 86 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 87 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 88 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 89 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 90 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 91 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 92 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 93 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 94 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 95 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 96 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 97 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 98 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 99 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 100 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 101 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 102 PCIE4, PCIE4, PCIE4, PCIE4} }, 103 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 104 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 105 PCIE4, PCIE4, PCIE4, PCIE4} }, 106 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 107 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 108 PCIE4, PCIE4, PCIE4, PCIE4} }, 109 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, 110 XFI_FM1_MAC1, XFI_FM1_MAC2, 111 PCIE4, PCIE4, PCIE4, PCIE4} }, 112 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, 113 PCIE4, PCIE4, PCIE4, PCIE4} }, 114 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, 115 PCIE3, PCIE3, PCIE3, PCIE3} }, 116 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 117 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 118 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 119 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 120 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 121 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 122 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 123 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 124 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 125 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 126 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 127 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 128 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, 129 XFI_FM1_MAC1, XFI_FM1_MAC2, 130 PCIE4, PCIE4, PCIE4, PCIE4} }, 131 132 #elif defined(CONFIG_PPC_T2081) 133 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, 134 PCIE4, PCIE4, PCIE4, PCIE4} }, 135 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 136 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 137 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 138 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, 139 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 140 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 141 #endif 142 {} 143 }; 144 145 #ifndef CONFIG_PPC_T2081 146 static const struct serdes_config serdes2_cfg_tbl[] = { 147 /* SerDes 2 */ 148 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, 149 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 150 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 151 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 152 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 153 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 154 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, 155 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 156 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, 157 {} 158 }; 159 #endif 160 161 static const struct serdes_config *serdes_cfg_tbl[] = { 162 serdes1_cfg_tbl, 163 #ifndef CONFIG_PPC_T2081 164 serdes2_cfg_tbl, 165 #endif 166 }; 167 168 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 169 { 170 const struct serdes_config *ptr; 171 172 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 173 return 0; 174 175 ptr = serdes_cfg_tbl[serdes]; 176 while (ptr->protocol) { 177 if (ptr->protocol == cfg) 178 return ptr->lanes[lane]; 179 ptr++; 180 } 181 return 0; 182 } 183 184 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 185 { 186 int i; 187 const struct serdes_config *ptr; 188 189 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 190 return 0; 191 192 ptr = serdes_cfg_tbl[serdes]; 193 while (ptr->protocol) { 194 if (ptr->protocol == prtcl) 195 break; 196 ptr++; 197 } 198 199 if (!ptr->protocol) 200 return 0; 201 202 for (i = 0; i < SRDS_MAX_LANES; i++) { 203 if (ptr->lanes[i] != NONE) 204 return 1; 205 } 206 207 return 0; 208 } 209