1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/fsl_serdes.h> 11 #include <asm/processor.h> 12 #include "fsl_corenet2_serdes.h" 13 14 struct serdes_config { 15 u32 protocol; 16 u8 lanes[SRDS_MAX_LANES]; 17 }; 18 19 static const struct serdes_config serdes1_cfg_tbl[] = { 20 /* SerDes 1 */ 21 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, 22 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 23 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 24 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, 25 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, 26 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 27 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 28 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 29 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 30 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 31 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 32 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, 33 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 34 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, 35 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 36 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 37 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 38 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 39 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 40 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 41 SGMII_FM1_DTSEC2, PCIE4, PCIE1, 42 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 43 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, 44 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 45 PCIE4, PCIE4, PCIE4, PCIE4} }, 46 {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 49 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 50 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 52 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 53 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 54 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 55 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 57 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 58 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 59 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 61 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 62 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 63 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 64 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 65 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 66 {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 67 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 68 PCIE4, SGMII_FM1_DTSEC4, 69 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 70 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 71 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 72 PCIE4, SGMII_FM1_DTSEC4, 73 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 74 {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 75 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 76 PCIE4, SGMII_FM1_DTSEC4, 77 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 78 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 79 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 80 PCIE4, SGMII_FM1_DTSEC4, 81 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 82 {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 83 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 84 PCIE4, SGMII_FM1_DTSEC4, 85 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 86 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 87 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 88 PCIE4, SGMII_FM1_DTSEC4, 89 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 90 {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10, 91 XFI_FM1_MAC1, XFI_FM1_MAC2, 92 PCIE4, SGMII_FM1_DTSEC4, 93 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 94 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, 95 XFI_FM1_MAC1, XFI_FM1_MAC2, 96 PCIE4, SGMII_FM1_DTSEC4, 97 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 98 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, 99 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 100 PCIE4, PCIE4, PCIE4, PCIE4} }, 101 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, 102 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 103 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 104 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 105 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 106 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 107 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 108 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 109 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 110 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 111 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 112 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 113 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 114 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 115 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 116 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 117 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 118 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 119 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 120 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 121 PCIE4, PCIE4, PCIE4, PCIE4} }, 122 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 123 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 124 PCIE4, PCIE4, PCIE4, PCIE4} }, 125 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 126 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 127 PCIE4, PCIE4, PCIE4, PCIE4} }, 128 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, 129 XFI_FM1_MAC1, XFI_FM1_MAC2, 130 PCIE4, PCIE4, PCIE4, PCIE4} }, 131 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, 132 PCIE4, PCIE4, PCIE4, PCIE4} }, 133 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, 134 PCIE3, PCIE3, PCIE3, PCIE3} }, 135 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 136 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 137 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 138 {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 139 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 140 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 141 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 142 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 143 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 144 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 145 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 146 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 147 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 148 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 149 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 150 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, 151 XFI_FM1_MAC1, XFI_FM1_MAC2, 152 PCIE4, PCIE4, PCIE4, PCIE4} }, 153 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, 154 PCIE4, PCIE4, PCIE4, PCIE4} }, 155 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 156 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 157 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 158 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, 159 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 160 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 161 {} 162 }; 163 164 #ifndef CONFIG_ARCH_T2081 165 static const struct serdes_config serdes2_cfg_tbl[] = { 166 /* SerDes 2 */ 167 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, 168 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 169 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 170 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 171 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 172 {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 173 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 174 {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} }, 175 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, 176 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 177 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, 178 {} 179 }; 180 #endif 181 182 static const struct serdes_config *serdes_cfg_tbl[] = { 183 serdes1_cfg_tbl, 184 #ifndef CONFIG_ARCH_T2081 185 serdes2_cfg_tbl, 186 #endif 187 }; 188 189 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 190 { 191 const struct serdes_config *ptr; 192 193 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 194 return 0; 195 196 ptr = serdes_cfg_tbl[serdes]; 197 while (ptr->protocol) { 198 if (ptr->protocol == cfg) 199 return ptr->lanes[lane]; 200 ptr++; 201 } 202 return 0; 203 } 204 205 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 206 { 207 int i; 208 const struct serdes_config *ptr; 209 210 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 211 return 0; 212 213 ptr = serdes_cfg_tbl[serdes]; 214 while (ptr->protocol) { 215 if (ptr->protocol == prtcl) 216 break; 217 ptr++; 218 } 219 220 if (!ptr->protocol) 221 return 0; 222 223 for (i = 0; i < SRDS_MAX_LANES; i++) { 224 if (ptr->lanes[i] != NONE) 225 return 1; 226 } 227 228 return 0; 229 } 230