1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2012 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/fsl_serdes.h>
8 #include <asm/processor.h>
9 #include <asm/io.h>
10 
11 
12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
13 	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
14 		PCIE2, PCIE2, PCIE2, PCIE2},
15 	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
16 		PCIE2, PCIE3, PCIE4, SATA1},
17 	[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
18 		PCIE2, PCIE3, SATA2, SATA1},
19 	[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
20 		PCIE2, PCIE2, PCIE2, PCIE2},
21 	[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
22 		PCIE2, PCIE2, PCIE2, PCIE2},
23 	[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
24 		PCIE2, PCIE3, PCIE4, SATA1},
25 	[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
26 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
27 	[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
28 		PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
29 	[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
30 		PCIE2, PCIE3, PCIE4, SATA1},
31 	[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
32 		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
33 	[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
34 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
35 	[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
36 		PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
37 	[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
38 		PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
39 	[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
40 		AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
41 	[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
42 		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
43 	[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 		 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
45 	[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
46 		 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
47 };
48 
49 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
50 {
51 	return serdes_cfg_tbl[cfg][lane];
52 }
53 
54 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
55 {
56 	int i;
57 
58 	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
59 		return 0;
60 
61 	for (i = 0; i < SRDS_MAX_LANES; i++) {
62 		if (serdes_cfg_tbl[prtcl][i] != NONE)
63 			return 1;
64 	}
65 
66 	return 0;
67 }
68