1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet2_serdes.h" 28 29 static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = { 30 { /* SerDes 1 */ 31 [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, 32 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, 33 [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, 34 PCIE2, PCIE3, PCIE4, SATA1}, 35 [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, 36 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, 37 [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, 38 PCIE2, PCIE2, PCIE2, PCIE2}, 39 [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, 40 PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5}, 41 [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, 42 PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1}, 43 [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 44 PCIE2, PCIE3, PCIE4, SATA1}, 45 [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 46 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, 47 [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 48 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, 49 [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 50 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, 51 [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 52 PCIE2, PCIE2, PCIE2, PCIE2}, 53 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, 54 PCIE2, PCIE3, PCIE4, SATA1}, 55 [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, 56 PCIE2, PCIE3, SATA2, SATA1}, 57 [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 58 AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, 59 [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 60 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, 61 [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 62 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, 63 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, 64 PCIE2, PCIE2, PCIE2, PCIE2}, 65 }, 66 { 67 }, 68 { 69 }, 70 { 71 }, 72 }; 73 74 75 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 76 { 77 return serdes_cfg_tbl[serdes][cfg][lane]; 78 } 79 80 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 81 { 82 int i; 83 84 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes])) 85 return 0; 86 87 for (i = 0; i < SRDS_MAX_LANES; i++) { 88 if (serdes_cfg_tbl[serdes][prtcl][i] != NONE) 89 return 1; 90 } 91 92 return 0; 93 } 94