1/* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25 * 26 * The processor starts at 0xfffffffc and the code is first executed in the 27 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28 * 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <mpc85xx.h> 34#include <version.h> 35 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#undef MSR_KERNEL 45#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46 47/* 48 * Set up GOT: Global Offset Table 49 * 50 * Use r12 to access the GOT 51 */ 52 START_GOT 53 GOT_ENTRY(_GOT2_TABLE_) 54 GOT_ENTRY(_FIXUP_TABLE_) 55 56#ifndef CONFIG_NAND_SPL 57 GOT_ENTRY(_start) 58 GOT_ENTRY(_start_of_vectors) 59 GOT_ENTRY(_end_of_vectors) 60 GOT_ENTRY(transfer_to_handler) 61#endif 62 63 GOT_ENTRY(__init_end) 64 GOT_ENTRY(__bss_end__) 65 GOT_ENTRY(__bss_start) 66 END_GOT 67 68/* 69 * e500 Startup -- after reset only the last 4KB of the effective 70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71 * section is located at THIS LAST page and basically does three 72 * things: clear some registers, set up exception tables and 73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74 * continue the boot procedure. 75 76 * Once the boot rom is mapped by TLB entries we can proceed 77 * with normal startup. 78 * 79 */ 80 81 .section .bootpg,"ax" 82 .globl _start_e500 83 84_start_e500: 85 86#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 87 /* ISBC uses L2 as stack. 88 * Disable L2 cache here so that u-boot can enable it later 89 * as part of it's normal flow 90 */ 91 92 /* Check if L2 is enabled */ 93 mfspr r3, SPRN_L2CSR0 94 lis r2, L2CSR0_L2E@h 95 ori r2, r2, L2CSR0_L2E@l 96 and. r4, r3, r2 97 beq l2_disabled 98 99 mfspr r3, SPRN_L2CSR0 100 /* Flush L2 cache */ 101 lis r2,(L2CSR0_L2FL)@h 102 ori r2, r2, (L2CSR0_L2FL)@l 103 or r3, r2, r3 104 sync 105 isync 106 mtspr SPRN_L2CSR0,r3 107 isync 1081: 109 mfspr r3, SPRN_L2CSR0 110 and. r1, r3, r2 111 bne 1b 112 113 mfspr r3, SPRN_L2CSR0 114 lis r2, L2CSR0_L2E@h 115 ori r2, r2, L2CSR0_L2E@l 116 andc r4, r3, r2 117 sync 118 isync 119 mtspr SPRN_L2CSR0,r4 120 isync 121 122l2_disabled: 123#endif 124 125/* clear registers/arrays not reset by hardware */ 126 127 /* L1 */ 128 li r0,2 129 mtspr L1CSR0,r0 /* invalidate d-cache */ 130 mtspr L1CSR1,r0 /* invalidate i-cache */ 131 132 mfspr r1,DBSR 133 mtspr DBSR,r1 /* Clear all valid bits */ 134 135 /* 136 * Enable L1 Caches early 137 * 138 */ 139 140#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 141 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 142 li r2,(32 + 0) 143 mtspr L1CSR2,r2 144#endif 145 146 /* Enable/invalidate the I-Cache */ 147 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 148 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 149 mtspr SPRN_L1CSR1,r2 1501: 151 mfspr r3,SPRN_L1CSR1 152 and. r1,r3,r2 153 bne 1b 154 155 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 156 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 157 mtspr SPRN_L1CSR1,r3 158 isync 1592: 160 mfspr r3,SPRN_L1CSR1 161 andi. r1,r3,L1CSR1_ICE@l 162 beq 2b 163 164 /* Enable/invalidate the D-Cache */ 165 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 166 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 167 mtspr SPRN_L1CSR0,r2 1681: 169 mfspr r3,SPRN_L1CSR0 170 and. r1,r3,r2 171 bne 1b 172 173 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 174 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 175 mtspr SPRN_L1CSR0,r3 176 isync 1772: 178 mfspr r3,SPRN_L1CSR0 179 andi. r1,r3,L1CSR0_DCE@l 180 beq 2b 181 182 /* Setup interrupt vectors */ 183 lis r1,CONFIG_SYS_MONITOR_BASE@h 184 mtspr IVPR,r1 185 186 li r1,0x0100 187 mtspr IVOR0,r1 /* 0: Critical input */ 188 li r1,0x0200 189 mtspr IVOR1,r1 /* 1: Machine check */ 190 li r1,0x0300 191 mtspr IVOR2,r1 /* 2: Data storage */ 192 li r1,0x0400 193 mtspr IVOR3,r1 /* 3: Instruction storage */ 194 li r1,0x0500 195 mtspr IVOR4,r1 /* 4: External interrupt */ 196 li r1,0x0600 197 mtspr IVOR5,r1 /* 5: Alignment */ 198 li r1,0x0700 199 mtspr IVOR6,r1 /* 6: Program check */ 200 li r1,0x0800 201 mtspr IVOR7,r1 /* 7: floating point unavailable */ 202 li r1,0x0900 203 mtspr IVOR8,r1 /* 8: System call */ 204 /* 9: Auxiliary processor unavailable(unsupported) */ 205 li r1,0x0a00 206 mtspr IVOR10,r1 /* 10: Decrementer */ 207 li r1,0x0b00 208 mtspr IVOR11,r1 /* 11: Interval timer */ 209 li r1,0x0c00 210 mtspr IVOR12,r1 /* 12: Watchdog timer */ 211 li r1,0x0d00 212 mtspr IVOR13,r1 /* 13: Data TLB error */ 213 li r1,0x0e00 214 mtspr IVOR14,r1 /* 14: Instruction TLB error */ 215 li r1,0x0f00 216 mtspr IVOR15,r1 /* 15: Debug */ 217 218 /* Clear and set up some registers. */ 219 li r0,0x0000 220 lis r1,0xffff 221 mtspr DEC,r0 /* prevent dec exceptions */ 222 mttbl r0 /* prevent fit & wdt exceptions */ 223 mttbu r0 224 mtspr TSR,r1 /* clear all timer exception status */ 225 mtspr TCR,r0 /* disable all */ 226 mtspr ESR,r0 /* clear exception syndrome register */ 227 mtspr MCSR,r0 /* machine check syndrome register */ 228 mtxer r0 /* clear integer exception register */ 229 230#ifdef CONFIG_SYS_BOOK3E_HV 231 mtspr MAS8,r0 /* make sure MAS8 is clear */ 232#endif 233 234 /* Enable Time Base and Select Time Base Clock */ 235 lis r0,HID0_EMCP@h /* Enable machine check */ 236#if defined(CONFIG_ENABLE_36BIT_PHYS) 237 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 238#endif 239#ifndef CONFIG_E500MC 240 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 241#endif 242 mtspr HID0,r0 243 244#ifndef CONFIG_E500MC 245 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 246 mfspr r3,PVR 247 andi. r3,r3, 0xff 248 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 249 blt 1f 250 /* Set MBDD bit also */ 251 ori r0, r0, HID1_MBDD@l 2521: 253 mtspr HID1,r0 254#endif 255 256 /* Enable Branch Prediction */ 257#if defined(CONFIG_BTB) 258 lis r0,BUCSR_ENABLE@h 259 ori r0,r0,BUCSR_ENABLE@l 260 mtspr SPRN_BUCSR,r0 261#endif 262 263#if defined(CONFIG_SYS_INIT_DBCR) 264 lis r1,0xffff 265 ori r1,r1,0xffff 266 mtspr DBSR,r1 /* Clear all status bits */ 267 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 268 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 269 mtspr DBCR0,r0 270#endif 271 272#ifdef CONFIG_MPC8569 273#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 274#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 275 276 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 277 * use address space which is more than 12bits, and it must be done in 278 * the 4K boot page. So we set this bit here. 279 */ 280 281 /* create a temp mapping TLB0[0] for LBCR */ 282 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 283 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 284 285 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 286 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 287 288 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 289 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 290 291 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 292 (MAS3_SX|MAS3_SW|MAS3_SR))@h 293 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 294 (MAS3_SX|MAS3_SW|MAS3_SR))@l 295 296 mtspr MAS0,r6 297 mtspr MAS1,r7 298 mtspr MAS2,r8 299 mtspr MAS3,r9 300 isync 301 msync 302 tlbwe 303 304 /* Set LBCR register */ 305 lis r4,CONFIG_SYS_LBCR_ADDR@h 306 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 307 308 lis r5,CONFIG_SYS_LBC_LBCR@h 309 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 310 stw r5,0(r4) 311 isync 312 313 /* invalidate this temp TLB */ 314 lis r4,CONFIG_SYS_LBC_ADDR@h 315 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 316 tlbivax 0,r4 317 isync 318 319#endif /* CONFIG_MPC8569 */ 320 321/* 322 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 323 * location is not where we want it. This typically happens on a 36-bit 324 * system, where we want to move CCSR to near the top of 36-bit address space. 325 * 326 * To move CCSR, we create two temporary TLBs, one for the old location, and 327 * another for the new location. On CoreNet systems, we also need to create 328 * a special, temporary LAW. 329 * 330 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 331 * long-term TLBs, so we use TLB0 here. 332 */ 333#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 334 335#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 336#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 337#endif 338 339purge_old_ccsr_tlb: 340 lis r8, CONFIG_SYS_CCSRBAR@h 341 ori r8, r8, CONFIG_SYS_CCSRBAR@l 342 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 343 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 344 345 /* 346 * In a multi-stage boot (e.g. NAND boot), a previous stage may have 347 * created a TLB for CCSR, which will interfere with our relocation 348 * code. Since we're going to create a new TLB for CCSR anyway, 349 * it should be safe to delete this old TLB here. We have to search 350 * for it, though. 351 */ 352 353 li r1, 0 354 mtspr MAS6, r1 /* Search the current address space and PID */ 355 tlbsx 0, r8 356 mfspr r1, MAS1 357 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 358 beq 1f /* Skip if no TLB found */ 359 360 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 361 mtspr MAS1, r1 362 tlbwe 3631: 364 365create_ccsr_new_tlb: 366 /* 367 * Create a TLB for the new location of CCSR. Register R8 is reserved 368 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 369 */ 370 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 371 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 372 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 373 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 374 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 375 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 376 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 377 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 378 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 379 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 380 mtspr MAS0, r0 381 mtspr MAS1, r1 382 mtspr MAS2, r2 383 mtspr MAS3, r3 384 mtspr MAS7, r7 385 isync 386 msync 387 tlbwe 388 389 /* 390 * Create a TLB for the old location of CCSR. Register R9 is reserved 391 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 392 */ 393create_ccsr_old_tlb: 394 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 395 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 396 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 397 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 398 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 399 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 400 li r7, 0 /* The default CCSR address is always a 32-bit number */ 401 mtspr MAS0, r0 402 /* MAS1 is the same as above */ 403 mtspr MAS2, r2 404 mtspr MAS3, r3 405 mtspr MAS7, r7 406 isync 407 msync 408 tlbwe 409 410#ifdef CONFIG_FSL_CORENET 411 412#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 413#define LAW_EN 0x80000000 414#define LAW_SIZE_4K 0xb 415#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 416#define CCSRAR_C 0x80000000 /* Commit */ 417 418create_temp_law: 419 /* 420 * On CoreNet systems, we create the temporary LAW using a special LAW 421 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 422 */ 423 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 424 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 425 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 426 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 427 lis r2, CCSRBAR_LAWAR@h 428 ori r2, r2, CCSRBAR_LAWAR@l 429 430 stw r0, 0xc00(r9) /* LAWBARH0 */ 431 stw r1, 0xc04(r9) /* LAWBARL0 */ 432 sync 433 stw r2, 0xc08(r9) /* LAWAR0 */ 434 435 /* 436 * Read back from LAWAR to ensure the update is complete. e500mc 437 * cores also require an isync. 438 */ 439 lwz r0, 0xc08(r9) /* LAWAR0 */ 440 isync 441 442 /* 443 * Read the current CCSRBARH and CCSRBARL using load word instructions. 444 * Follow this with an isync instruction. This forces any outstanding 445 * accesses to configuration space to completion. 446 */ 447read_old_ccsrbar: 448 lwz r0, 0(r9) /* CCSRBARH */ 449 lwz r0, 4(r9) /* CCSRBARH */ 450 isync 451 452 /* 453 * Write the new values for CCSRBARH and CCSRBARL to their old 454 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 455 * has a new value written it loads a CCSRBARH shadow register. When 456 * the CCSRBARL is written, the CCSRBARH shadow register contents 457 * along with the CCSRBARL value are loaded into the CCSRBARH and 458 * CCSRBARL registers, respectively. Follow this with a sync 459 * instruction. 460 */ 461write_new_ccsrbar: 462 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 463 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 464 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 465 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 466 lis r2, CCSRAR_C@h 467 ori r2, r2, CCSRAR_C@l 468 469 stw r0, 0(r9) /* Write to CCSRBARH */ 470 sync /* Make sure we write to CCSRBARH first */ 471 stw r1, 4(r9) /* Write to CCSRBARL */ 472 sync 473 474 /* 475 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 476 * Follow this with a sync instruction. 477 */ 478 stw r2, 8(r9) 479 sync 480 481 /* Delete the temporary LAW */ 482delete_temp_law: 483 li r1, 0 484 stw r1, 0xc08(r8) 485 sync 486 stw r1, 0xc00(r8) 487 stw r1, 0xc04(r8) 488 sync 489 490#else /* #ifdef CONFIG_FSL_CORENET */ 491 492write_new_ccsrbar: 493 /* 494 * Read the current value of CCSRBAR using a load word instruction 495 * followed by an isync. This forces all accesses to configuration 496 * space to complete. 497 */ 498 sync 499 lwz r0, 0(r9) 500 isync 501 502/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 503#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 504 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 505 506 /* Write the new value to CCSRBAR. */ 507 lis r0, CCSRBAR_PHYS_RS12@h 508 ori r0, r0, CCSRBAR_PHYS_RS12@l 509 stw r0, 0(r9) 510 sync 511 512 /* 513 * The manual says to perform a load of an address that does not 514 * access configuration space or the on-chip SRAM using an existing TLB, 515 * but that doesn't appear to be necessary. We will do the isync, 516 * though. 517 */ 518 isync 519 520 /* 521 * Read the contents of CCSRBAR from its new location, followed by 522 * another isync. 523 */ 524 lwz r0, 0(r8) 525 isync 526 527#endif /* #ifdef CONFIG_FSL_CORENET */ 528 529 /* Delete the temporary TLBs */ 530delete_temp_tlbs: 531 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 532 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 533 li r1, 0 534 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 535 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 536 mtspr MAS0, r0 537 mtspr MAS1, r1 538 mtspr MAS2, r2 539 isync 540 msync 541 tlbwe 542 543 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 544 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 545 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 546 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 547 mtspr MAS0, r0 548 mtspr MAS2, r2 549 isync 550 msync 551 tlbwe 552#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 553 554create_init_ram_area: 555 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 556 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 557 558#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 559 /* create a temp mapping in AS=1 to the 4M boot window */ 560 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 561 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 562 563 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 564 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 565 566 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 567 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 568 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 569#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 570 /* create a temp mapping in AS = 1 for Flash mapping 571 * created by PBL for ISBC code 572 */ 573 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 574 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 575 576 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 577 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 578 579 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 580 (MAS3_SX|MAS3_SW|MAS3_SR))@h 581 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 582 (MAS3_SX|MAS3_SW|MAS3_SR))@l 583#else 584 /* 585 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 586 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 587 */ 588 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 589 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 590 591 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 592 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 593 594 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 595 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 596#endif 597 598 mtspr MAS0,r6 599 mtspr MAS1,r7 600 mtspr MAS2,r8 601 mtspr MAS3,r9 602 isync 603 msync 604 tlbwe 605 606 /* create a temp mapping in AS=1 to the stack */ 607 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 608 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 609 610 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 611 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 612 613 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 614 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 615 616#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 617 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 618 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 619 (MAS3_SX|MAS3_SW|MAS3_SR))@h 620 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 621 (MAS3_SX|MAS3_SW|MAS3_SR))@l 622 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 623 mtspr MAS7,r10 624#else 625 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 626 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 627#endif 628 629 mtspr MAS0,r6 630 mtspr MAS1,r7 631 mtspr MAS2,r8 632 mtspr MAS3,r9 633 isync 634 msync 635 tlbwe 636 637 lis r6,MSR_IS|MSR_DS@h 638 ori r6,r6,MSR_IS|MSR_DS@l 639 lis r7,switch_as@h 640 ori r7,r7,switch_as@l 641 642 mtspr SPRN_SRR0,r7 643 mtspr SPRN_SRR1,r6 644 rfi 645 646switch_as: 647/* L1 DCache is used for initial RAM */ 648 649 /* Allocate Initial RAM in data cache. 650 */ 651 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 652 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 653 mfspr r2, L1CFG0 654 andi. r2, r2, 0x1ff 655 /* cache size * 1024 / (2 * L1 line size) */ 656 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 657 mtctr r2 658 li r0,0 6591: 660 dcbz r0,r3 661 dcbtls 0,r0,r3 662 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 663 bdnz 1b 664 665 /* Jump out the last 4K page and continue to 'normal' start */ 666#ifdef CONFIG_SYS_RAMBOOT 667 b _start_cont 668#else 669 /* Calculate absolute address in FLASH and jump there */ 670 /*--------------------------------------------------------------*/ 671 lis r3,CONFIG_SYS_MONITOR_BASE@h 672 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 673 addi r3,r3,_start_cont - _start + _START_OFFSET 674 mtlr r3 675 blr 676#endif 677 678 .text 679 .globl _start 680_start: 681 .long 0x27051956 /* U-BOOT Magic Number */ 682 .globl version_string 683version_string: 684 .ascii U_BOOT_VERSION_STRING, "\0" 685 686 .align 4 687 .globl _start_cont 688_start_cont: 689 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 690 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 691 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 692 693 li r0,0 694 stwu r0,-4(r1) 695 stwu r0,-4(r1) /* Terminate call chain */ 696 697 stwu r1,-8(r1) /* Save back chain and move SP */ 698 lis r0,RESET_VECTOR@h /* Address of reset vector */ 699 ori r0,r0,RESET_VECTOR@l 700 stwu r1,-8(r1) /* Save back chain and move SP */ 701 stw r0,+12(r1) /* Save return addr (underflow vect) */ 702 703 GET_GOT 704 bl cpu_init_early_f 705 706 /* switch back to AS = 0 */ 707 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 708 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 709 mtmsr r3 710 isync 711 712 bl cpu_init_f 713 bl board_init_f 714 isync 715 716 /* NOTREACHED - board_init_f() does not return */ 717 718#ifndef CONFIG_NAND_SPL 719 . = EXC_OFF_SYS_RESET 720 .globl _start_of_vectors 721_start_of_vectors: 722 723/* Critical input. */ 724 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 725 726/* Machine check */ 727 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 728 729/* Data Storage exception. */ 730 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 731 732/* Instruction Storage exception. */ 733 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 734 735/* External Interrupt exception. */ 736 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 737 738/* Alignment exception. */ 739 . = 0x0600 740Alignment: 741 EXCEPTION_PROLOG(SRR0, SRR1) 742 mfspr r4,DAR 743 stw r4,_DAR(r21) 744 mfspr r5,DSISR 745 stw r5,_DSISR(r21) 746 addi r3,r1,STACK_FRAME_OVERHEAD 747 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 748 749/* Program check exception */ 750 . = 0x0700 751ProgramCheck: 752 EXCEPTION_PROLOG(SRR0, SRR1) 753 addi r3,r1,STACK_FRAME_OVERHEAD 754 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 755 MSR_KERNEL, COPY_EE) 756 757 /* No FPU on MPC85xx. This exception is not supposed to happen. 758 */ 759 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 760 761 . = 0x0900 762/* 763 * r0 - SYSCALL number 764 * r3-... arguments 765 */ 766SystemCall: 767 addis r11,r0,0 /* get functions table addr */ 768 ori r11,r11,0 /* Note: this code is patched in trap_init */ 769 addis r12,r0,0 /* get number of functions */ 770 ori r12,r12,0 771 772 cmplw 0,r0,r12 773 bge 1f 774 775 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 776 add r11,r11,r0 777 lwz r11,0(r11) 778 779 li r20,0xd00-4 /* Get stack pointer */ 780 lwz r12,0(r20) 781 subi r12,r12,12 /* Adjust stack pointer */ 782 li r0,0xc00+_end_back-SystemCall 783 cmplw 0,r0,r12 /* Check stack overflow */ 784 bgt 1f 785 stw r12,0(r20) 786 787 mflr r0 788 stw r0,0(r12) 789 mfspr r0,SRR0 790 stw r0,4(r12) 791 mfspr r0,SRR1 792 stw r0,8(r12) 793 794 li r12,0xc00+_back-SystemCall 795 mtlr r12 796 mtspr SRR0,r11 797 7981: SYNC 799 rfi 800_back: 801 802 mfmsr r11 /* Disable interrupts */ 803 li r12,0 804 ori r12,r12,MSR_EE 805 andc r11,r11,r12 806 SYNC /* Some chip revs need this... */ 807 mtmsr r11 808 SYNC 809 810 li r12,0xd00-4 /* restore regs */ 811 lwz r12,0(r12) 812 813 lwz r11,0(r12) 814 mtlr r11 815 lwz r11,4(r12) 816 mtspr SRR0,r11 817 lwz r11,8(r12) 818 mtspr SRR1,r11 819 820 addi r12,r12,12 /* Adjust stack pointer */ 821 li r20,0xd00-4 822 stw r12,0(r20) 823 824 SYNC 825 rfi 826_end_back: 827 828 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 829 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 830 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 831 832 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 833 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 834 835 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 836 837 .globl _end_of_vectors 838_end_of_vectors: 839 840 841 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 842 843/* 844 * This code finishes saving the registers to the exception frame 845 * and jumps to the appropriate handler for the exception. 846 * Register r21 is pointer into trap frame, r1 has new stack pointer. 847 */ 848 .globl transfer_to_handler 849transfer_to_handler: 850 stw r22,_NIP(r21) 851 lis r22,MSR_POW@h 852 andc r23,r23,r22 853 stw r23,_MSR(r21) 854 SAVE_GPR(7, r21) 855 SAVE_4GPRS(8, r21) 856 SAVE_8GPRS(12, r21) 857 SAVE_8GPRS(24, r21) 858 859 mflr r23 860 andi. r24,r23,0x3f00 /* get vector offset */ 861 stw r24,TRAP(r21) 862 li r22,0 863 stw r22,RESULT(r21) 864 mtspr SPRG2,r22 /* r1 is now kernel sp */ 865 866 lwz r24,0(r23) /* virtual address of handler */ 867 lwz r23,4(r23) /* where to go when done */ 868 mtspr SRR0,r24 869 mtspr SRR1,r20 870 mtlr r23 871 SYNC 872 rfi /* jump to handler, enable MMU */ 873 874int_return: 875 mfmsr r28 /* Disable interrupts */ 876 li r4,0 877 ori r4,r4,MSR_EE 878 andc r28,r28,r4 879 SYNC /* Some chip revs need this... */ 880 mtmsr r28 881 SYNC 882 lwz r2,_CTR(r1) 883 lwz r0,_LINK(r1) 884 mtctr r2 885 mtlr r0 886 lwz r2,_XER(r1) 887 lwz r0,_CCR(r1) 888 mtspr XER,r2 889 mtcrf 0xFF,r0 890 REST_10GPRS(3, r1) 891 REST_10GPRS(13, r1) 892 REST_8GPRS(23, r1) 893 REST_GPR(31, r1) 894 lwz r2,_NIP(r1) /* Restore environment */ 895 lwz r0,_MSR(r1) 896 mtspr SRR0,r2 897 mtspr SRR1,r0 898 lwz r0,GPR0(r1) 899 lwz r2,GPR2(r1) 900 lwz r1,GPR1(r1) 901 SYNC 902 rfi 903 904crit_return: 905 mfmsr r28 /* Disable interrupts */ 906 li r4,0 907 ori r4,r4,MSR_EE 908 andc r28,r28,r4 909 SYNC /* Some chip revs need this... */ 910 mtmsr r28 911 SYNC 912 lwz r2,_CTR(r1) 913 lwz r0,_LINK(r1) 914 mtctr r2 915 mtlr r0 916 lwz r2,_XER(r1) 917 lwz r0,_CCR(r1) 918 mtspr XER,r2 919 mtcrf 0xFF,r0 920 REST_10GPRS(3, r1) 921 REST_10GPRS(13, r1) 922 REST_8GPRS(23, r1) 923 REST_GPR(31, r1) 924 lwz r2,_NIP(r1) /* Restore environment */ 925 lwz r0,_MSR(r1) 926 mtspr SPRN_CSRR0,r2 927 mtspr SPRN_CSRR1,r0 928 lwz r0,GPR0(r1) 929 lwz r2,GPR2(r1) 930 lwz r1,GPR1(r1) 931 SYNC 932 rfci 933 934mck_return: 935 mfmsr r28 /* Disable interrupts */ 936 li r4,0 937 ori r4,r4,MSR_EE 938 andc r28,r28,r4 939 SYNC /* Some chip revs need this... */ 940 mtmsr r28 941 SYNC 942 lwz r2,_CTR(r1) 943 lwz r0,_LINK(r1) 944 mtctr r2 945 mtlr r0 946 lwz r2,_XER(r1) 947 lwz r0,_CCR(r1) 948 mtspr XER,r2 949 mtcrf 0xFF,r0 950 REST_10GPRS(3, r1) 951 REST_10GPRS(13, r1) 952 REST_8GPRS(23, r1) 953 REST_GPR(31, r1) 954 lwz r2,_NIP(r1) /* Restore environment */ 955 lwz r0,_MSR(r1) 956 mtspr SPRN_MCSRR0,r2 957 mtspr SPRN_MCSRR1,r0 958 lwz r0,GPR0(r1) 959 lwz r2,GPR2(r1) 960 lwz r1,GPR1(r1) 961 SYNC 962 rfmci 963 964/* Cache functions. 965*/ 966.globl flush_icache 967flush_icache: 968.globl invalidate_icache 969invalidate_icache: 970 mfspr r0,L1CSR1 971 ori r0,r0,L1CSR1_ICFI 972 msync 973 isync 974 mtspr L1CSR1,r0 975 isync 976 blr /* entire I cache */ 977 978.globl invalidate_dcache 979invalidate_dcache: 980 mfspr r0,L1CSR0 981 ori r0,r0,L1CSR0_DCFI 982 msync 983 isync 984 mtspr L1CSR0,r0 985 isync 986 blr 987 988 .globl icache_enable 989icache_enable: 990 mflr r8 991 bl invalidate_icache 992 mtlr r8 993 isync 994 mfspr r4,L1CSR1 995 ori r4,r4,0x0001 996 oris r4,r4,0x0001 997 mtspr L1CSR1,r4 998 isync 999 blr 1000 1001 .globl icache_disable 1002icache_disable: 1003 mfspr r0,L1CSR1 1004 lis r3,0 1005 ori r3,r3,L1CSR1_ICE 1006 andc r0,r0,r3 1007 mtspr L1CSR1,r0 1008 isync 1009 blr 1010 1011 .globl icache_status 1012icache_status: 1013 mfspr r3,L1CSR1 1014 andi. r3,r3,L1CSR1_ICE 1015 blr 1016 1017 .globl dcache_enable 1018dcache_enable: 1019 mflr r8 1020 bl invalidate_dcache 1021 mtlr r8 1022 isync 1023 mfspr r0,L1CSR0 1024 ori r0,r0,0x0001 1025 oris r0,r0,0x0001 1026 msync 1027 isync 1028 mtspr L1CSR0,r0 1029 isync 1030 blr 1031 1032 .globl dcache_disable 1033dcache_disable: 1034 mfspr r3,L1CSR0 1035 lis r4,0 1036 ori r4,r4,L1CSR0_DCE 1037 andc r3,r3,r4 1038 mtspr L1CSR0,r3 1039 isync 1040 blr 1041 1042 .globl dcache_status 1043dcache_status: 1044 mfspr r3,L1CSR0 1045 andi. r3,r3,L1CSR0_DCE 1046 blr 1047 1048 .globl get_pir 1049get_pir: 1050 mfspr r3,PIR 1051 blr 1052 1053 .globl get_pvr 1054get_pvr: 1055 mfspr r3,PVR 1056 blr 1057 1058 .globl get_svr 1059get_svr: 1060 mfspr r3,SVR 1061 blr 1062 1063 .globl wr_tcr 1064wr_tcr: 1065 mtspr TCR,r3 1066 blr 1067 1068/*------------------------------------------------------------------------------- */ 1069/* Function: in8 */ 1070/* Description: Input 8 bits */ 1071/*------------------------------------------------------------------------------- */ 1072 .globl in8 1073in8: 1074 lbz r3,0x0000(r3) 1075 blr 1076 1077/*------------------------------------------------------------------------------- */ 1078/* Function: out8 */ 1079/* Description: Output 8 bits */ 1080/*------------------------------------------------------------------------------- */ 1081 .globl out8 1082out8: 1083 stb r4,0x0000(r3) 1084 sync 1085 blr 1086 1087/*------------------------------------------------------------------------------- */ 1088/* Function: out16 */ 1089/* Description: Output 16 bits */ 1090/*------------------------------------------------------------------------------- */ 1091 .globl out16 1092out16: 1093 sth r4,0x0000(r3) 1094 sync 1095 blr 1096 1097/*------------------------------------------------------------------------------- */ 1098/* Function: out16r */ 1099/* Description: Byte reverse and output 16 bits */ 1100/*------------------------------------------------------------------------------- */ 1101 .globl out16r 1102out16r: 1103 sthbrx r4,r0,r3 1104 sync 1105 blr 1106 1107/*------------------------------------------------------------------------------- */ 1108/* Function: out32 */ 1109/* Description: Output 32 bits */ 1110/*------------------------------------------------------------------------------- */ 1111 .globl out32 1112out32: 1113 stw r4,0x0000(r3) 1114 sync 1115 blr 1116 1117/*------------------------------------------------------------------------------- */ 1118/* Function: out32r */ 1119/* Description: Byte reverse and output 32 bits */ 1120/*------------------------------------------------------------------------------- */ 1121 .globl out32r 1122out32r: 1123 stwbrx r4,r0,r3 1124 sync 1125 blr 1126 1127/*------------------------------------------------------------------------------- */ 1128/* Function: in16 */ 1129/* Description: Input 16 bits */ 1130/*------------------------------------------------------------------------------- */ 1131 .globl in16 1132in16: 1133 lhz r3,0x0000(r3) 1134 blr 1135 1136/*------------------------------------------------------------------------------- */ 1137/* Function: in16r */ 1138/* Description: Input 16 bits and byte reverse */ 1139/*------------------------------------------------------------------------------- */ 1140 .globl in16r 1141in16r: 1142 lhbrx r3,r0,r3 1143 blr 1144 1145/*------------------------------------------------------------------------------- */ 1146/* Function: in32 */ 1147/* Description: Input 32 bits */ 1148/*------------------------------------------------------------------------------- */ 1149 .globl in32 1150in32: 1151 lwz 3,0x0000(3) 1152 blr 1153 1154/*------------------------------------------------------------------------------- */ 1155/* Function: in32r */ 1156/* Description: Input 32 bits and byte reverse */ 1157/*------------------------------------------------------------------------------- */ 1158 .globl in32r 1159in32r: 1160 lwbrx r3,r0,r3 1161 blr 1162#endif /* !CONFIG_NAND_SPL */ 1163 1164/*------------------------------------------------------------------------------*/ 1165 1166/* 1167 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1168 */ 1169 .globl write_tlb 1170write_tlb: 1171 mtspr MAS0,r3 1172 mtspr MAS1,r4 1173 mtspr MAS2,r5 1174 mtspr MAS3,r6 1175#ifdef CONFIG_ENABLE_36BIT_PHYS 1176 mtspr MAS7,r7 1177#endif 1178 li r3,0 1179#ifdef CONFIG_SYS_BOOK3E_HV 1180 mtspr MAS8,r3 1181#endif 1182 isync 1183 tlbwe 1184 msync 1185 isync 1186 blr 1187 1188/* 1189 * void relocate_code (addr_sp, gd, addr_moni) 1190 * 1191 * This "function" does not return, instead it continues in RAM 1192 * after relocating the monitor code. 1193 * 1194 * r3 = dest 1195 * r4 = src 1196 * r5 = length in bytes 1197 * r6 = cachelinesize 1198 */ 1199 .globl relocate_code 1200relocate_code: 1201 mr r1,r3 /* Set new stack pointer */ 1202 mr r9,r4 /* Save copy of Init Data pointer */ 1203 mr r10,r5 /* Save copy of Destination Address */ 1204 1205 GET_GOT 1206 mr r3,r5 /* Destination Address */ 1207 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1208 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1209 lwz r5,GOT(__init_end) 1210 sub r5,r5,r4 1211 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1212 1213 /* 1214 * Fix GOT pointer: 1215 * 1216 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1217 * 1218 * Offset: 1219 */ 1220 sub r15,r10,r4 1221 1222 /* First our own GOT */ 1223 add r12,r12,r15 1224 /* the the one used by the C code */ 1225 add r30,r30,r15 1226 1227 /* 1228 * Now relocate code 1229 */ 1230 1231 cmplw cr1,r3,r4 1232 addi r0,r5,3 1233 srwi. r0,r0,2 1234 beq cr1,4f /* In place copy is not necessary */ 1235 beq 7f /* Protect against 0 count */ 1236 mtctr r0 1237 bge cr1,2f 1238 1239 la r8,-4(r4) 1240 la r7,-4(r3) 12411: lwzu r0,4(r8) 1242 stwu r0,4(r7) 1243 bdnz 1b 1244 b 4f 1245 12462: slwi r0,r0,2 1247 add r8,r4,r0 1248 add r7,r3,r0 12493: lwzu r0,-4(r8) 1250 stwu r0,-4(r7) 1251 bdnz 3b 1252 1253/* 1254 * Now flush the cache: note that we must start from a cache aligned 1255 * address. Otherwise we might miss one cache line. 1256 */ 12574: cmpwi r6,0 1258 add r5,r3,r5 1259 beq 7f /* Always flush prefetch queue in any case */ 1260 subi r0,r6,1 1261 andc r3,r3,r0 1262 mr r4,r3 12635: dcbst 0,r4 1264 add r4,r4,r6 1265 cmplw r4,r5 1266 blt 5b 1267 sync /* Wait for all dcbst to complete on bus */ 1268 mr r4,r3 12696: icbi 0,r4 1270 add r4,r4,r6 1271 cmplw r4,r5 1272 blt 6b 12737: sync /* Wait for all icbi to complete on bus */ 1274 isync 1275 1276 /* 1277 * Re-point the IVPR at RAM 1278 */ 1279 mtspr IVPR,r10 1280 1281/* 1282 * We are done. Do not return, instead branch to second part of board 1283 * initialization, now running from RAM. 1284 */ 1285 1286 addi r0,r10,in_ram - _start + _START_OFFSET 1287 mtlr r0 1288 blr /* NEVER RETURNS! */ 1289 .globl in_ram 1290in_ram: 1291 1292 /* 1293 * Relocation Function, r12 point to got2+0x8000 1294 * 1295 * Adjust got2 pointers, no need to check for 0, this code 1296 * already puts a few entries in the table. 1297 */ 1298 li r0,__got2_entries@sectoff@l 1299 la r3,GOT(_GOT2_TABLE_) 1300 lwz r11,GOT(_GOT2_TABLE_) 1301 mtctr r0 1302 sub r11,r3,r11 1303 addi r3,r3,-4 13041: lwzu r0,4(r3) 1305 cmpwi r0,0 1306 beq- 2f 1307 add r0,r0,r11 1308 stw r0,0(r3) 13092: bdnz 1b 1310 1311 /* 1312 * Now adjust the fixups and the pointers to the fixups 1313 * in case we need to move ourselves again. 1314 */ 1315 li r0,__fixup_entries@sectoff@l 1316 lwz r3,GOT(_FIXUP_TABLE_) 1317 cmpwi r0,0 1318 mtctr r0 1319 addi r3,r3,-4 1320 beq 4f 13213: lwzu r4,4(r3) 1322 lwzux r0,r4,r11 1323 cmpwi r0,0 1324 add r0,r0,r11 1325 stw r4,0(r3) 1326 beq- 5f 1327 stw r0,0(r4) 13285: bdnz 3b 13294: 1330clear_bss: 1331 /* 1332 * Now clear BSS segment 1333 */ 1334 lwz r3,GOT(__bss_start) 1335 lwz r4,GOT(__bss_end__) 1336 1337 cmplw 0,r3,r4 1338 beq 6f 1339 1340 li r0,0 13415: 1342 stw r0,0(r3) 1343 addi r3,r3,4 1344 cmplw 0,r3,r4 1345 bne 5b 13466: 1347 1348 mr r3,r9 /* Init Data pointer */ 1349 mr r4,r10 /* Destination Address */ 1350 bl board_init_r 1351 1352#ifndef CONFIG_NAND_SPL 1353 /* 1354 * Copy exception vector code to low memory 1355 * 1356 * r3: dest_addr 1357 * r7: source address, r8: end address, r9: target address 1358 */ 1359 .globl trap_init 1360trap_init: 1361 mflr r4 /* save link register */ 1362 GET_GOT 1363 lwz r7,GOT(_start_of_vectors) 1364 lwz r8,GOT(_end_of_vectors) 1365 1366 li r9,0x100 /* reset vector always at 0x100 */ 1367 1368 cmplw 0,r7,r8 1369 bgelr /* return if r7>=r8 - just in case */ 13701: 1371 lwz r0,0(r7) 1372 stw r0,0(r9) 1373 addi r7,r7,4 1374 addi r9,r9,4 1375 cmplw 0,r7,r8 1376 bne 1b 1377 1378 /* 1379 * relocate `hdlr' and `int_return' entries 1380 */ 1381 li r7,.L_CriticalInput - _start + _START_OFFSET 1382 bl trap_reloc 1383 li r7,.L_MachineCheck - _start + _START_OFFSET 1384 bl trap_reloc 1385 li r7,.L_DataStorage - _start + _START_OFFSET 1386 bl trap_reloc 1387 li r7,.L_InstStorage - _start + _START_OFFSET 1388 bl trap_reloc 1389 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1390 bl trap_reloc 1391 li r7,.L_Alignment - _start + _START_OFFSET 1392 bl trap_reloc 1393 li r7,.L_ProgramCheck - _start + _START_OFFSET 1394 bl trap_reloc 1395 li r7,.L_FPUnavailable - _start + _START_OFFSET 1396 bl trap_reloc 1397 li r7,.L_Decrementer - _start + _START_OFFSET 1398 bl trap_reloc 1399 li r7,.L_IntervalTimer - _start + _START_OFFSET 1400 li r8,_end_of_vectors - _start + _START_OFFSET 14012: 1402 bl trap_reloc 1403 addi r7,r7,0x100 /* next exception vector */ 1404 cmplw 0,r7,r8 1405 blt 2b 1406 1407 lis r7,0x0 1408 mtspr IVPR,r7 1409 1410 mtlr r4 /* restore link register */ 1411 blr 1412 1413.globl unlock_ram_in_cache 1414unlock_ram_in_cache: 1415 /* invalidate the INIT_RAM section */ 1416 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1417 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1418 mfspr r4,L1CFG0 1419 andi. r4,r4,0x1ff 1420 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1421 mtctr r4 14221: dcbi r0,r3 1423 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1424 bdnz 1b 1425 sync 1426 1427 /* Invalidate the TLB entries for the cache */ 1428 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1429 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1430 tlbivax 0,r3 1431 addi r3,r3,0x1000 1432 tlbivax 0,r3 1433 addi r3,r3,0x1000 1434 tlbivax 0,r3 1435 addi r3,r3,0x1000 1436 tlbivax 0,r3 1437 isync 1438 blr 1439 1440.globl flush_dcache 1441flush_dcache: 1442 mfspr r3,SPRN_L1CFG0 1443 1444 rlwinm r5,r3,9,3 /* Extract cache block size */ 1445 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1446 * are currently defined. 1447 */ 1448 li r4,32 1449 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1450 * log2(number of ways) 1451 */ 1452 slw r5,r4,r5 /* r5 = cache block size */ 1453 1454 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1455 mulli r7,r7,13 /* An 8-way cache will require 13 1456 * loads per set. 1457 */ 1458 slw r7,r7,r6 1459 1460 /* save off HID0 and set DCFA */ 1461 mfspr r8,SPRN_HID0 1462 ori r9,r8,HID0_DCFA@l 1463 mtspr SPRN_HID0,r9 1464 isync 1465 1466 lis r4,0 1467 mtctr r7 1468 14691: lwz r3,0(r4) /* Load... */ 1470 add r4,r4,r5 1471 bdnz 1b 1472 1473 msync 1474 lis r4,0 1475 mtctr r7 1476 14771: dcbf 0,r4 /* ...and flush. */ 1478 add r4,r4,r5 1479 bdnz 1b 1480 1481 /* restore HID0 */ 1482 mtspr SPRN_HID0,r8 1483 isync 1484 1485 blr 1486 1487.globl setup_ivors 1488setup_ivors: 1489 1490#include "fixed_ivor.S" 1491 blr 1492#endif /* !CONFIG_NAND_SPL */ 1493