1/* 2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25 * 26 * The processor starts at 0xfffffffc and the code is first executed in the 27 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28 * 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <mpc85xx.h> 34#include <version.h> 35 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#undef MSR_KERNEL 45#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46 47/* 48 * Set up GOT: Global Offset Table 49 * 50 * Use r12 to access the GOT 51 */ 52 START_GOT 53 GOT_ENTRY(_GOT2_TABLE_) 54 GOT_ENTRY(_FIXUP_TABLE_) 55 56#ifndef CONFIG_NAND_SPL 57 GOT_ENTRY(_start) 58 GOT_ENTRY(_start_of_vectors) 59 GOT_ENTRY(_end_of_vectors) 60 GOT_ENTRY(transfer_to_handler) 61#endif 62 63 GOT_ENTRY(__init_end) 64 GOT_ENTRY(__bss_end__) 65 GOT_ENTRY(__bss_start) 66 END_GOT 67 68/* 69 * e500 Startup -- after reset only the last 4KB of the effective 70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71 * section is located at THIS LAST page and basically does three 72 * things: clear some registers, set up exception tables and 73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74 * continue the boot procedure. 75 76 * Once the boot rom is mapped by TLB entries we can proceed 77 * with normal startup. 78 * 79 */ 80 81 .section .bootpg,"ax" 82 .globl _start_e500 83 84_start_e500: 85/* Enable debug exception */ 86 li r1,MSR_DE 87 mtmsr r1 88 89#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 90 /* ISBC uses L2 as stack. 91 * Disable L2 cache here so that u-boot can enable it later 92 * as part of it's normal flow 93 */ 94 95 /* Check if L2 is enabled */ 96 mfspr r3, SPRN_L2CSR0 97 lis r2, L2CSR0_L2E@h 98 ori r2, r2, L2CSR0_L2E@l 99 and. r4, r3, r2 100 beq l2_disabled 101 102 mfspr r3, SPRN_L2CSR0 103 /* Flush L2 cache */ 104 lis r2,(L2CSR0_L2FL)@h 105 ori r2, r2, (L2CSR0_L2FL)@l 106 or r3, r2, r3 107 sync 108 isync 109 mtspr SPRN_L2CSR0,r3 110 isync 1111: 112 mfspr r3, SPRN_L2CSR0 113 and. r1, r3, r2 114 bne 1b 115 116 mfspr r3, SPRN_L2CSR0 117 lis r2, L2CSR0_L2E@h 118 ori r2, r2, L2CSR0_L2E@l 119 andc r4, r3, r2 120 sync 121 isync 122 mtspr SPRN_L2CSR0,r4 123 isync 124 125l2_disabled: 126#endif 127 128/* clear registers/arrays not reset by hardware */ 129 130 /* L1 */ 131 li r0,2 132 mtspr L1CSR0,r0 /* invalidate d-cache */ 133 mtspr L1CSR1,r0 /* invalidate i-cache */ 134 135 mfspr r1,DBSR 136 mtspr DBSR,r1 /* Clear all valid bits */ 137 138 /* 139 * Enable L1 Caches early 140 * 141 */ 142 143#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 144 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 145 li r2,(32 + 0) 146 mtspr L1CSR2,r2 147#endif 148 149 /* Enable/invalidate the I-Cache */ 150 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 151 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 152 mtspr SPRN_L1CSR1,r2 1531: 154 mfspr r3,SPRN_L1CSR1 155 and. r1,r3,r2 156 bne 1b 157 158 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 159 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 160 mtspr SPRN_L1CSR1,r3 161 isync 1622: 163 mfspr r3,SPRN_L1CSR1 164 andi. r1,r3,L1CSR1_ICE@l 165 beq 2b 166 167 /* Enable/invalidate the D-Cache */ 168 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 169 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 170 mtspr SPRN_L1CSR0,r2 1711: 172 mfspr r3,SPRN_L1CSR0 173 and. r1,r3,r2 174 bne 1b 175 176 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 177 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 178 mtspr SPRN_L1CSR0,r3 179 isync 1802: 181 mfspr r3,SPRN_L1CSR0 182 andi. r1,r3,L1CSR0_DCE@l 183 beq 2b 184 185#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) 186/* 187 * TLB entry for debuggging in AS1 188 * Create temporary TLB entry in AS0 to handle debug exception 189 * As on debug exception MSR is cleared i.e. Address space is changed 190 * to 0. A TLB entry (in AS0) is required to handle debug exception generated 191 * in AS1. 192 */ 193 194 lis r6,FSL_BOOKE_MAS0(1, 195 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h 196 ori r6,r6,FSL_BOOKE_MAS0(1, 197 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l 198 199#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 200/* 201 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 202 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. 203 * and this window is outside of 4K boot window. 204 */ 205 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h 206 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l 207 208 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 209 (MAS2_I|MAS2_G))@h 210 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 211 (MAS2_I|MAS2_G))@l 212 213 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 214 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 215 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 216#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 217 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 218 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 219 220 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h 221 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l 222 223 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 224 (MAS3_SX|MAS3_SW|MAS3_SR))@h 225 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 226 (MAS3_SX|MAS3_SW|MAS3_SR))@l 227#else 228/* 229 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 230 * because "nexti" will resize TLB to 4K 231 */ 232 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h 233 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l 234 235 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h 236 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, 237 (MAS2_I))@l 238 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 239 (MAS3_SX|MAS3_SW|MAS3_SR))@h 240 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 241 (MAS3_SX|MAS3_SW|MAS3_SR))@l 242#endif 243 mtspr MAS0,r6 244 mtspr MAS1,r7 245 mtspr MAS2,r8 246 mtspr MAS3,r9 247 tlbwe 248 isync 249#endif 250 251/* 252 * Ne need to setup interrupt vector for NAND SPL 253 * because NAND SPL never compiles it. 254 */ 255#if !defined(CONFIG_NAND_SPL) 256 /* Setup interrupt vectors */ 257 lis r1,CONFIG_SYS_MONITOR_BASE@h 258 mtspr IVPR,r1 259 260 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h 261 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l 262 263 addi r4,r3,CriticalInput - _start + _START_OFFSET 264 mtspr IVOR0,r4 /* 0: Critical input */ 265 addi r4,r3,MachineCheck - _start + _START_OFFSET 266 mtspr IVOR1,r4 /* 1: Machine check */ 267 addi r4,r3,DataStorage - _start + _START_OFFSET 268 mtspr IVOR2,r4 /* 2: Data storage */ 269 addi r4,r3,InstStorage - _start + _START_OFFSET 270 mtspr IVOR3,r4 /* 3: Instruction storage */ 271 addi r4,r3,ExtInterrupt - _start + _START_OFFSET 272 mtspr IVOR4,r4 /* 4: External interrupt */ 273 addi r4,r3,Alignment - _start + _START_OFFSET 274 mtspr IVOR5,r4 /* 5: Alignment */ 275 addi r4,r3,ProgramCheck - _start + _START_OFFSET 276 mtspr IVOR6,r4 /* 6: Program check */ 277 addi r4,r3,FPUnavailable - _start + _START_OFFSET 278 mtspr IVOR7,r4 /* 7: floating point unavailable */ 279 addi r4,r3,SystemCall - _start + _START_OFFSET 280 mtspr IVOR8,r4 /* 8: System call */ 281 /* 9: Auxiliary processor unavailable(unsupported) */ 282 addi r4,r3,Decrementer - _start + _START_OFFSET 283 mtspr IVOR10,r4 /* 10: Decrementer */ 284 addi r4,r3,IntervalTimer - _start + _START_OFFSET 285 mtspr IVOR11,r4 /* 11: Interval timer */ 286 addi r4,r3,WatchdogTimer - _start + _START_OFFSET 287 mtspr IVOR12,r4 /* 12: Watchdog timer */ 288 addi r4,r3,DataTLBError - _start + _START_OFFSET 289 mtspr IVOR13,r4 /* 13: Data TLB error */ 290 addi r4,r3,InstructionTLBError - _start + _START_OFFSET 291 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 292 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET 293 mtspr IVOR15,r4 /* 15: Debug */ 294#endif 295 296 /* Clear and set up some registers. */ 297 li r0,0x0000 298 lis r1,0xffff 299 mtspr DEC,r0 /* prevent dec exceptions */ 300 mttbl r0 /* prevent fit & wdt exceptions */ 301 mttbu r0 302 mtspr TSR,r1 /* clear all timer exception status */ 303 mtspr TCR,r0 /* disable all */ 304 mtspr ESR,r0 /* clear exception syndrome register */ 305 mtspr MCSR,r0 /* machine check syndrome register */ 306 mtxer r0 /* clear integer exception register */ 307 308#ifdef CONFIG_SYS_BOOK3E_HV 309 mtspr MAS8,r0 /* make sure MAS8 is clear */ 310#endif 311 312 /* Enable Time Base and Select Time Base Clock */ 313 lis r0,HID0_EMCP@h /* Enable machine check */ 314#if defined(CONFIG_ENABLE_36BIT_PHYS) 315 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 316#endif 317#ifndef CONFIG_E500MC 318 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 319#endif 320 mtspr HID0,r0 321 322#ifndef CONFIG_E500MC 323 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 324 mfspr r3,PVR 325 andi. r3,r3, 0xff 326 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 327 blt 1f 328 /* Set MBDD bit also */ 329 ori r0, r0, HID1_MBDD@l 3301: 331 mtspr HID1,r0 332#endif 333 334#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 335 mfspr r3,977 336 oris r3,r3,0x0100 337 mtspr 977,r3 338#endif 339 340 /* Enable Branch Prediction */ 341#if defined(CONFIG_BTB) 342 lis r0,BUCSR_ENABLE@h 343 ori r0,r0,BUCSR_ENABLE@l 344 mtspr SPRN_BUCSR,r0 345#endif 346 347#if defined(CONFIG_SYS_INIT_DBCR) 348 lis r1,0xffff 349 ori r1,r1,0xffff 350 mtspr DBSR,r1 /* Clear all status bits */ 351 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 352 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 353 mtspr DBCR0,r0 354#endif 355 356#ifdef CONFIG_MPC8569 357#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 358#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 359 360 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 361 * use address space which is more than 12bits, and it must be done in 362 * the 4K boot page. So we set this bit here. 363 */ 364 365 /* create a temp mapping TLB0[0] for LBCR */ 366 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 367 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 368 369 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 370 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 371 372 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 373 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 374 375 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 376 (MAS3_SX|MAS3_SW|MAS3_SR))@h 377 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 378 (MAS3_SX|MAS3_SW|MAS3_SR))@l 379 380 mtspr MAS0,r6 381 mtspr MAS1,r7 382 mtspr MAS2,r8 383 mtspr MAS3,r9 384 isync 385 msync 386 tlbwe 387 388 /* Set LBCR register */ 389 lis r4,CONFIG_SYS_LBCR_ADDR@h 390 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 391 392 lis r5,CONFIG_SYS_LBC_LBCR@h 393 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 394 stw r5,0(r4) 395 isync 396 397 /* invalidate this temp TLB */ 398 lis r4,CONFIG_SYS_LBC_ADDR@h 399 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 400 tlbivax 0,r4 401 isync 402 403#endif /* CONFIG_MPC8569 */ 404 405/* 406 * Search for the TLB that covers the code we're executing, and shrink it 407 * so that it covers only this 4K page. That will ensure that any other 408 * TLB we create won't interfere with it. We assume that the TLB exists, 409 * which is why we don't check the Valid bit of MAS1. 410 * 411 * This is necessary, for example, when booting from the on-chip ROM, 412 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 413 * If we don't shrink this TLB now, then we'll accidentally delete it 414 * in "purge_old_ccsr_tlb" below. 415 */ 416 bl nexti /* Find our address */ 417nexti: mflr r1 /* R1 = our PC */ 418 li r2, 0 419 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 420 isync 421 msync 422 tlbsx 0, r1 /* This must succeed */ 423 424 /* Set the size of the TLB to 4KB */ 425 mfspr r3, MAS1 426 li r2, 0xF00 427 andc r3, r3, r2 /* Clear the TSIZE bits */ 428 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 429 mtspr MAS1, r3 430 431 /* 432 * Set the base address of the TLB to our PC. We assume that 433 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 434 */ 435 lis r3, MAS2_EPN@h 436 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 437 438 and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 439 440 mfspr r2, MAS2 441 andc r2, r2, r3 442 or r2, r2, r1 443 mtspr MAS2, r2 /* Set the EPN to our PC base address */ 444 445 mfspr r2, MAS3 446 andc r2, r2, r3 447 or r2, r2, r1 448 mtspr MAS3, r2 /* Set the RPN to our PC base address */ 449 450 isync 451 msync 452 tlbwe 453 454/* 455 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 456 * location is not where we want it. This typically happens on a 36-bit 457 * system, where we want to move CCSR to near the top of 36-bit address space. 458 * 459 * To move CCSR, we create two temporary TLBs, one for the old location, and 460 * another for the new location. On CoreNet systems, we also need to create 461 * a special, temporary LAW. 462 * 463 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 464 * long-term TLBs, so we use TLB0 here. 465 */ 466#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 467 468#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 469#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 470#endif 471 472purge_old_ccsr_tlb: 473 lis r8, CONFIG_SYS_CCSRBAR@h 474 ori r8, r8, CONFIG_SYS_CCSRBAR@l 475 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 476 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 477 478 /* 479 * In a multi-stage boot (e.g. NAND boot), a previous stage may have 480 * created a TLB for CCSR, which will interfere with our relocation 481 * code. Since we're going to create a new TLB for CCSR anyway, 482 * it should be safe to delete this old TLB here. We have to search 483 * for it, though. 484 */ 485 486 li r1, 0 487 mtspr MAS6, r1 /* Search the current address space and PID */ 488 isync 489 msync 490 tlbsx 0, r8 491 mfspr r1, MAS1 492 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 493 beq 1f /* Skip if no TLB found */ 494 495 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 496 mtspr MAS1, r1 497 isync 498 msync 499 tlbwe 5001: 501 502create_ccsr_new_tlb: 503 /* 504 * Create a TLB for the new location of CCSR. Register R8 is reserved 505 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 506 */ 507 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 508 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 509 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 510 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 511 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 512 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 513 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 514 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 515#ifdef CONFIG_ENABLE_36BIT_PHYS 516 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 517 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 518 mtspr MAS7, r7 519#endif 520 mtspr MAS0, r0 521 mtspr MAS1, r1 522 mtspr MAS2, r2 523 mtspr MAS3, r3 524 isync 525 msync 526 tlbwe 527 528 /* 529 * Create a TLB for the current location of CCSR. Register R9 is reserved 530 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 531 */ 532create_ccsr_old_tlb: 533 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 534 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 535 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 536 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 537 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 538 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 539#ifdef CONFIG_ENABLE_36BIT_PHYS 540 li r7, 0 /* The default CCSR address is always a 32-bit number */ 541 mtspr MAS7, r7 542#endif 543 mtspr MAS0, r0 544 /* MAS1 is the same as above */ 545 mtspr MAS2, r2 546 mtspr MAS3, r3 547 isync 548 msync 549 tlbwe 550 551 /* 552 * We have a TLB for what we think is the current (old) CCSR. Let's 553 * verify that, otherwise we won't be able to move it. 554 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 555 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 556 */ 557verify_old_ccsr: 558 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 559 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 560#ifdef CONFIG_FSL_CORENET 561 lwz r1, 4(r9) /* CCSRBARL */ 562#else 563 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 564 slwi r1, r1, 12 565#endif 566 567 cmpl 0, r0, r1 568 569 /* 570 * If the value we read from CCSRBARL is not what we expect, then 571 * enter an infinite loop. This will at least allow a debugger to 572 * halt execution and examine TLBs, etc. There's no point in going 573 * on. 574 */ 575infinite_debug_loop: 576 bne infinite_debug_loop 577 578#ifdef CONFIG_FSL_CORENET 579 580#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 581#define LAW_EN 0x80000000 582#define LAW_SIZE_4K 0xb 583#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 584#define CCSRAR_C 0x80000000 /* Commit */ 585 586create_temp_law: 587 /* 588 * On CoreNet systems, we create the temporary LAW using a special LAW 589 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 590 */ 591 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 592 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 593 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 594 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 595 lis r2, CCSRBAR_LAWAR@h 596 ori r2, r2, CCSRBAR_LAWAR@l 597 598 stw r0, 0xc00(r9) /* LAWBARH0 */ 599 stw r1, 0xc04(r9) /* LAWBARL0 */ 600 sync 601 stw r2, 0xc08(r9) /* LAWAR0 */ 602 603 /* 604 * Read back from LAWAR to ensure the update is complete. e500mc 605 * cores also require an isync. 606 */ 607 lwz r0, 0xc08(r9) /* LAWAR0 */ 608 isync 609 610 /* 611 * Read the current CCSRBARH and CCSRBARL using load word instructions. 612 * Follow this with an isync instruction. This forces any outstanding 613 * accesses to configuration space to completion. 614 */ 615read_old_ccsrbar: 616 lwz r0, 0(r9) /* CCSRBARH */ 617 lwz r0, 4(r9) /* CCSRBARL */ 618 isync 619 620 /* 621 * Write the new values for CCSRBARH and CCSRBARL to their old 622 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 623 * has a new value written it loads a CCSRBARH shadow register. When 624 * the CCSRBARL is written, the CCSRBARH shadow register contents 625 * along with the CCSRBARL value are loaded into the CCSRBARH and 626 * CCSRBARL registers, respectively. Follow this with a sync 627 * instruction. 628 */ 629write_new_ccsrbar: 630 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 631 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 632 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 633 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 634 lis r2, CCSRAR_C@h 635 ori r2, r2, CCSRAR_C@l 636 637 stw r0, 0(r9) /* Write to CCSRBARH */ 638 sync /* Make sure we write to CCSRBARH first */ 639 stw r1, 4(r9) /* Write to CCSRBARL */ 640 sync 641 642 /* 643 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 644 * Follow this with a sync instruction. 645 */ 646 stw r2, 8(r9) 647 sync 648 649 /* Delete the temporary LAW */ 650delete_temp_law: 651 li r1, 0 652 stw r1, 0xc08(r8) 653 sync 654 stw r1, 0xc00(r8) 655 stw r1, 0xc04(r8) 656 sync 657 658#else /* #ifdef CONFIG_FSL_CORENET */ 659 660write_new_ccsrbar: 661 /* 662 * Read the current value of CCSRBAR using a load word instruction 663 * followed by an isync. This forces all accesses to configuration 664 * space to complete. 665 */ 666 sync 667 lwz r0, 0(r9) 668 isync 669 670/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 671#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 672 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 673 674 /* Write the new value to CCSRBAR. */ 675 lis r0, CCSRBAR_PHYS_RS12@h 676 ori r0, r0, CCSRBAR_PHYS_RS12@l 677 stw r0, 0(r9) 678 sync 679 680 /* 681 * The manual says to perform a load of an address that does not 682 * access configuration space or the on-chip SRAM using an existing TLB, 683 * but that doesn't appear to be necessary. We will do the isync, 684 * though. 685 */ 686 isync 687 688 /* 689 * Read the contents of CCSRBAR from its new location, followed by 690 * another isync. 691 */ 692 lwz r0, 0(r8) 693 isync 694 695#endif /* #ifdef CONFIG_FSL_CORENET */ 696 697 /* Delete the temporary TLBs */ 698delete_temp_tlbs: 699 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 700 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 701 li r1, 0 702 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 703 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 704 mtspr MAS0, r0 705 mtspr MAS1, r1 706 mtspr MAS2, r2 707 isync 708 msync 709 tlbwe 710 711 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 712 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 713 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 714 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 715 mtspr MAS0, r0 716 mtspr MAS2, r2 717 isync 718 msync 719 tlbwe 720#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 721 722create_init_ram_area: 723 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 724 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 725 726#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 727 /* create a temp mapping in AS=1 to the 4M boot window */ 728 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 729 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 730 731 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 732 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 733 734 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 735 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 736 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 737#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 738 /* create a temp mapping in AS = 1 for Flash mapping 739 * created by PBL for ISBC code 740 */ 741 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 742 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 743 744 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 745 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 746 747 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 748 (MAS3_SX|MAS3_SW|MAS3_SR))@h 749 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 750 (MAS3_SX|MAS3_SW|MAS3_SR))@l 751#else 752 /* 753 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 754 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 755 */ 756 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 757 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 758 759 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 760 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 761 762 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 763 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 764#endif 765 766 mtspr MAS0,r6 767 mtspr MAS1,r7 768 mtspr MAS2,r8 769 mtspr MAS3,r9 770 isync 771 msync 772 tlbwe 773 774 /* create a temp mapping in AS=1 to the stack */ 775 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 776 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 777 778 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 779 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 780 781 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 782 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 783 784#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 785 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 786 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 787 (MAS3_SX|MAS3_SW|MAS3_SR))@h 788 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 789 (MAS3_SX|MAS3_SW|MAS3_SR))@l 790 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 791 mtspr MAS7,r10 792#else 793 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 794 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 795#endif 796 797 mtspr MAS0,r6 798 mtspr MAS1,r7 799 mtspr MAS2,r8 800 mtspr MAS3,r9 801 isync 802 msync 803 tlbwe 804 805 lis r6,MSR_IS|MSR_DS|MSR_DE@h 806 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 807 lis r7,switch_as@h 808 ori r7,r7,switch_as@l 809 810 mtspr SPRN_SRR0,r7 811 mtspr SPRN_SRR1,r6 812 rfi 813 814switch_as: 815/* L1 DCache is used for initial RAM */ 816 817 /* Allocate Initial RAM in data cache. 818 */ 819 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 820 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 821 mfspr r2, L1CFG0 822 andi. r2, r2, 0x1ff 823 /* cache size * 1024 / (2 * L1 line size) */ 824 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 825 mtctr r2 826 li r0,0 8271: 828 dcbz r0,r3 829 dcbtls 0,r0,r3 830 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 831 bdnz 1b 832 833 /* Jump out the last 4K page and continue to 'normal' start */ 834#ifdef CONFIG_SYS_RAMBOOT 835 b _start_cont 836#else 837 /* Calculate absolute address in FLASH and jump there */ 838 /*--------------------------------------------------------------*/ 839 lis r3,CONFIG_SYS_MONITOR_BASE@h 840 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 841 addi r3,r3,_start_cont - _start + _START_OFFSET 842 mtlr r3 843 blr 844#endif 845 846 .text 847 .globl _start 848_start: 849 .long 0x27051956 /* U-BOOT Magic Number */ 850 .globl version_string 851version_string: 852 .ascii U_BOOT_VERSION_STRING, "\0" 853 854 .align 4 855 .globl _start_cont 856_start_cont: 857 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 858 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 859 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 860 861 li r0,0 862 stwu r0,-4(r1) 863 stwu r0,-4(r1) /* Terminate call chain */ 864 865 stwu r1,-8(r1) /* Save back chain and move SP */ 866 lis r0,RESET_VECTOR@h /* Address of reset vector */ 867 ori r0,r0,RESET_VECTOR@l 868 stwu r1,-8(r1) /* Save back chain and move SP */ 869 stw r0,+12(r1) /* Save return addr (underflow vect) */ 870 871 GET_GOT 872 bl cpu_init_early_f 873 874 /* switch back to AS = 0 */ 875 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 876 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 877 mtmsr r3 878 isync 879 880 bl cpu_init_f 881 bl board_init_f 882 isync 883 884 /* NOTREACHED - board_init_f() does not return */ 885 886#ifndef CONFIG_NAND_SPL 887 . = EXC_OFF_SYS_RESET 888 .globl _start_of_vectors 889_start_of_vectors: 890 891/* Critical input. */ 892 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 893 894/* Machine check */ 895 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 896 897/* Data Storage exception. */ 898 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 899 900/* Instruction Storage exception. */ 901 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 902 903/* External Interrupt exception. */ 904 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 905 906/* Alignment exception. */ 907 . = 0x0600 908Alignment: 909 EXCEPTION_PROLOG(SRR0, SRR1) 910 mfspr r4,DAR 911 stw r4,_DAR(r21) 912 mfspr r5,DSISR 913 stw r5,_DSISR(r21) 914 addi r3,r1,STACK_FRAME_OVERHEAD 915 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 916 917/* Program check exception */ 918 . = 0x0700 919ProgramCheck: 920 EXCEPTION_PROLOG(SRR0, SRR1) 921 addi r3,r1,STACK_FRAME_OVERHEAD 922 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 923 MSR_KERNEL, COPY_EE) 924 925 /* No FPU on MPC85xx. This exception is not supposed to happen. 926 */ 927 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 928 929 . = 0x0900 930/* 931 * r0 - SYSCALL number 932 * r3-... arguments 933 */ 934SystemCall: 935 addis r11,r0,0 /* get functions table addr */ 936 ori r11,r11,0 /* Note: this code is patched in trap_init */ 937 addis r12,r0,0 /* get number of functions */ 938 ori r12,r12,0 939 940 cmplw 0,r0,r12 941 bge 1f 942 943 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 944 add r11,r11,r0 945 lwz r11,0(r11) 946 947 li r20,0xd00-4 /* Get stack pointer */ 948 lwz r12,0(r20) 949 subi r12,r12,12 /* Adjust stack pointer */ 950 li r0,0xc00+_end_back-SystemCall 951 cmplw 0,r0,r12 /* Check stack overflow */ 952 bgt 1f 953 stw r12,0(r20) 954 955 mflr r0 956 stw r0,0(r12) 957 mfspr r0,SRR0 958 stw r0,4(r12) 959 mfspr r0,SRR1 960 stw r0,8(r12) 961 962 li r12,0xc00+_back-SystemCall 963 mtlr r12 964 mtspr SRR0,r11 965 9661: SYNC 967 rfi 968_back: 969 970 mfmsr r11 /* Disable interrupts */ 971 li r12,0 972 ori r12,r12,MSR_EE 973 andc r11,r11,r12 974 SYNC /* Some chip revs need this... */ 975 mtmsr r11 976 SYNC 977 978 li r12,0xd00-4 /* restore regs */ 979 lwz r12,0(r12) 980 981 lwz r11,0(r12) 982 mtlr r11 983 lwz r11,4(r12) 984 mtspr SRR0,r11 985 lwz r11,8(r12) 986 mtspr SRR1,r11 987 988 addi r12,r12,12 /* Adjust stack pointer */ 989 li r20,0xd00-4 990 stw r12,0(r20) 991 992 SYNC 993 rfi 994_end_back: 995 996 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 997 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 998 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 999 1000 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 1001 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 1002 1003 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 1004 1005 .globl _end_of_vectors 1006_end_of_vectors: 1007 1008 1009 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 1010 1011/* 1012 * This code finishes saving the registers to the exception frame 1013 * and jumps to the appropriate handler for the exception. 1014 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1015 */ 1016 .globl transfer_to_handler 1017transfer_to_handler: 1018 stw r22,_NIP(r21) 1019 lis r22,MSR_POW@h 1020 andc r23,r23,r22 1021 stw r23,_MSR(r21) 1022 SAVE_GPR(7, r21) 1023 SAVE_4GPRS(8, r21) 1024 SAVE_8GPRS(12, r21) 1025 SAVE_8GPRS(24, r21) 1026 1027 mflr r23 1028 andi. r24,r23,0x3f00 /* get vector offset */ 1029 stw r24,TRAP(r21) 1030 li r22,0 1031 stw r22,RESULT(r21) 1032 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1033 1034 lwz r24,0(r23) /* virtual address of handler */ 1035 lwz r23,4(r23) /* where to go when done */ 1036 mtspr SRR0,r24 1037 mtspr SRR1,r20 1038 mtlr r23 1039 SYNC 1040 rfi /* jump to handler, enable MMU */ 1041 1042int_return: 1043 mfmsr r28 /* Disable interrupts */ 1044 li r4,0 1045 ori r4,r4,MSR_EE 1046 andc r28,r28,r4 1047 SYNC /* Some chip revs need this... */ 1048 mtmsr r28 1049 SYNC 1050 lwz r2,_CTR(r1) 1051 lwz r0,_LINK(r1) 1052 mtctr r2 1053 mtlr r0 1054 lwz r2,_XER(r1) 1055 lwz r0,_CCR(r1) 1056 mtspr XER,r2 1057 mtcrf 0xFF,r0 1058 REST_10GPRS(3, r1) 1059 REST_10GPRS(13, r1) 1060 REST_8GPRS(23, r1) 1061 REST_GPR(31, r1) 1062 lwz r2,_NIP(r1) /* Restore environment */ 1063 lwz r0,_MSR(r1) 1064 mtspr SRR0,r2 1065 mtspr SRR1,r0 1066 lwz r0,GPR0(r1) 1067 lwz r2,GPR2(r1) 1068 lwz r1,GPR1(r1) 1069 SYNC 1070 rfi 1071 1072crit_return: 1073 mfmsr r28 /* Disable interrupts */ 1074 li r4,0 1075 ori r4,r4,MSR_EE 1076 andc r28,r28,r4 1077 SYNC /* Some chip revs need this... */ 1078 mtmsr r28 1079 SYNC 1080 lwz r2,_CTR(r1) 1081 lwz r0,_LINK(r1) 1082 mtctr r2 1083 mtlr r0 1084 lwz r2,_XER(r1) 1085 lwz r0,_CCR(r1) 1086 mtspr XER,r2 1087 mtcrf 0xFF,r0 1088 REST_10GPRS(3, r1) 1089 REST_10GPRS(13, r1) 1090 REST_8GPRS(23, r1) 1091 REST_GPR(31, r1) 1092 lwz r2,_NIP(r1) /* Restore environment */ 1093 lwz r0,_MSR(r1) 1094 mtspr SPRN_CSRR0,r2 1095 mtspr SPRN_CSRR1,r0 1096 lwz r0,GPR0(r1) 1097 lwz r2,GPR2(r1) 1098 lwz r1,GPR1(r1) 1099 SYNC 1100 rfci 1101 1102mck_return: 1103 mfmsr r28 /* Disable interrupts */ 1104 li r4,0 1105 ori r4,r4,MSR_EE 1106 andc r28,r28,r4 1107 SYNC /* Some chip revs need this... */ 1108 mtmsr r28 1109 SYNC 1110 lwz r2,_CTR(r1) 1111 lwz r0,_LINK(r1) 1112 mtctr r2 1113 mtlr r0 1114 lwz r2,_XER(r1) 1115 lwz r0,_CCR(r1) 1116 mtspr XER,r2 1117 mtcrf 0xFF,r0 1118 REST_10GPRS(3, r1) 1119 REST_10GPRS(13, r1) 1120 REST_8GPRS(23, r1) 1121 REST_GPR(31, r1) 1122 lwz r2,_NIP(r1) /* Restore environment */ 1123 lwz r0,_MSR(r1) 1124 mtspr SPRN_MCSRR0,r2 1125 mtspr SPRN_MCSRR1,r0 1126 lwz r0,GPR0(r1) 1127 lwz r2,GPR2(r1) 1128 lwz r1,GPR1(r1) 1129 SYNC 1130 rfmci 1131 1132/* Cache functions. 1133*/ 1134.globl flush_icache 1135flush_icache: 1136.globl invalidate_icache 1137invalidate_icache: 1138 mfspr r0,L1CSR1 1139 ori r0,r0,L1CSR1_ICFI 1140 msync 1141 isync 1142 mtspr L1CSR1,r0 1143 isync 1144 blr /* entire I cache */ 1145 1146.globl invalidate_dcache 1147invalidate_dcache: 1148 mfspr r0,L1CSR0 1149 ori r0,r0,L1CSR0_DCFI 1150 msync 1151 isync 1152 mtspr L1CSR0,r0 1153 isync 1154 blr 1155 1156 .globl icache_enable 1157icache_enable: 1158 mflr r8 1159 bl invalidate_icache 1160 mtlr r8 1161 isync 1162 mfspr r4,L1CSR1 1163 ori r4,r4,0x0001 1164 oris r4,r4,0x0001 1165 mtspr L1CSR1,r4 1166 isync 1167 blr 1168 1169 .globl icache_disable 1170icache_disable: 1171 mfspr r0,L1CSR1 1172 lis r3,0 1173 ori r3,r3,L1CSR1_ICE 1174 andc r0,r0,r3 1175 mtspr L1CSR1,r0 1176 isync 1177 blr 1178 1179 .globl icache_status 1180icache_status: 1181 mfspr r3,L1CSR1 1182 andi. r3,r3,L1CSR1_ICE 1183 blr 1184 1185 .globl dcache_enable 1186dcache_enable: 1187 mflr r8 1188 bl invalidate_dcache 1189 mtlr r8 1190 isync 1191 mfspr r0,L1CSR0 1192 ori r0,r0,0x0001 1193 oris r0,r0,0x0001 1194 msync 1195 isync 1196 mtspr L1CSR0,r0 1197 isync 1198 blr 1199 1200 .globl dcache_disable 1201dcache_disable: 1202 mfspr r3,L1CSR0 1203 lis r4,0 1204 ori r4,r4,L1CSR0_DCE 1205 andc r3,r3,r4 1206 mtspr L1CSR0,r3 1207 isync 1208 blr 1209 1210 .globl dcache_status 1211dcache_status: 1212 mfspr r3,L1CSR0 1213 andi. r3,r3,L1CSR0_DCE 1214 blr 1215 1216 .globl get_pir 1217get_pir: 1218 mfspr r3,PIR 1219 blr 1220 1221 .globl get_pvr 1222get_pvr: 1223 mfspr r3,PVR 1224 blr 1225 1226 .globl get_svr 1227get_svr: 1228 mfspr r3,SVR 1229 blr 1230 1231 .globl wr_tcr 1232wr_tcr: 1233 mtspr TCR,r3 1234 blr 1235 1236/*------------------------------------------------------------------------------- */ 1237/* Function: in8 */ 1238/* Description: Input 8 bits */ 1239/*------------------------------------------------------------------------------- */ 1240 .globl in8 1241in8: 1242 lbz r3,0x0000(r3) 1243 blr 1244 1245/*------------------------------------------------------------------------------- */ 1246/* Function: out8 */ 1247/* Description: Output 8 bits */ 1248/*------------------------------------------------------------------------------- */ 1249 .globl out8 1250out8: 1251 stb r4,0x0000(r3) 1252 sync 1253 blr 1254 1255/*------------------------------------------------------------------------------- */ 1256/* Function: out16 */ 1257/* Description: Output 16 bits */ 1258/*------------------------------------------------------------------------------- */ 1259 .globl out16 1260out16: 1261 sth r4,0x0000(r3) 1262 sync 1263 blr 1264 1265/*------------------------------------------------------------------------------- */ 1266/* Function: out16r */ 1267/* Description: Byte reverse and output 16 bits */ 1268/*------------------------------------------------------------------------------- */ 1269 .globl out16r 1270out16r: 1271 sthbrx r4,r0,r3 1272 sync 1273 blr 1274 1275/*------------------------------------------------------------------------------- */ 1276/* Function: out32 */ 1277/* Description: Output 32 bits */ 1278/*------------------------------------------------------------------------------- */ 1279 .globl out32 1280out32: 1281 stw r4,0x0000(r3) 1282 sync 1283 blr 1284 1285/*------------------------------------------------------------------------------- */ 1286/* Function: out32r */ 1287/* Description: Byte reverse and output 32 bits */ 1288/*------------------------------------------------------------------------------- */ 1289 .globl out32r 1290out32r: 1291 stwbrx r4,r0,r3 1292 sync 1293 blr 1294 1295/*------------------------------------------------------------------------------- */ 1296/* Function: in16 */ 1297/* Description: Input 16 bits */ 1298/*------------------------------------------------------------------------------- */ 1299 .globl in16 1300in16: 1301 lhz r3,0x0000(r3) 1302 blr 1303 1304/*------------------------------------------------------------------------------- */ 1305/* Function: in16r */ 1306/* Description: Input 16 bits and byte reverse */ 1307/*------------------------------------------------------------------------------- */ 1308 .globl in16r 1309in16r: 1310 lhbrx r3,r0,r3 1311 blr 1312 1313/*------------------------------------------------------------------------------- */ 1314/* Function: in32 */ 1315/* Description: Input 32 bits */ 1316/*------------------------------------------------------------------------------- */ 1317 .globl in32 1318in32: 1319 lwz 3,0x0000(3) 1320 blr 1321 1322/*------------------------------------------------------------------------------- */ 1323/* Function: in32r */ 1324/* Description: Input 32 bits and byte reverse */ 1325/*------------------------------------------------------------------------------- */ 1326 .globl in32r 1327in32r: 1328 lwbrx r3,r0,r3 1329 blr 1330#endif /* !CONFIG_NAND_SPL */ 1331 1332/*------------------------------------------------------------------------------*/ 1333 1334/* 1335 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1336 */ 1337 .globl write_tlb 1338write_tlb: 1339 mtspr MAS0,r3 1340 mtspr MAS1,r4 1341 mtspr MAS2,r5 1342 mtspr MAS3,r6 1343#ifdef CONFIG_ENABLE_36BIT_PHYS 1344 mtspr MAS7,r7 1345#endif 1346 li r3,0 1347#ifdef CONFIG_SYS_BOOK3E_HV 1348 mtspr MAS8,r3 1349#endif 1350 isync 1351 tlbwe 1352 msync 1353 isync 1354 blr 1355 1356/* 1357 * void relocate_code (addr_sp, gd, addr_moni) 1358 * 1359 * This "function" does not return, instead it continues in RAM 1360 * after relocating the monitor code. 1361 * 1362 * r3 = dest 1363 * r4 = src 1364 * r5 = length in bytes 1365 * r6 = cachelinesize 1366 */ 1367 .globl relocate_code 1368relocate_code: 1369 mr r1,r3 /* Set new stack pointer */ 1370 mr r9,r4 /* Save copy of Init Data pointer */ 1371 mr r10,r5 /* Save copy of Destination Address */ 1372 1373 GET_GOT 1374 mr r3,r5 /* Destination Address */ 1375 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1376 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1377 lwz r5,GOT(__init_end) 1378 sub r5,r5,r4 1379 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1380 1381 /* 1382 * Fix GOT pointer: 1383 * 1384 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1385 * 1386 * Offset: 1387 */ 1388 sub r15,r10,r4 1389 1390 /* First our own GOT */ 1391 add r12,r12,r15 1392 /* the the one used by the C code */ 1393 add r30,r30,r15 1394 1395 /* 1396 * Now relocate code 1397 */ 1398 1399 cmplw cr1,r3,r4 1400 addi r0,r5,3 1401 srwi. r0,r0,2 1402 beq cr1,4f /* In place copy is not necessary */ 1403 beq 7f /* Protect against 0 count */ 1404 mtctr r0 1405 bge cr1,2f 1406 1407 la r8,-4(r4) 1408 la r7,-4(r3) 14091: lwzu r0,4(r8) 1410 stwu r0,4(r7) 1411 bdnz 1b 1412 b 4f 1413 14142: slwi r0,r0,2 1415 add r8,r4,r0 1416 add r7,r3,r0 14173: lwzu r0,-4(r8) 1418 stwu r0,-4(r7) 1419 bdnz 3b 1420 1421/* 1422 * Now flush the cache: note that we must start from a cache aligned 1423 * address. Otherwise we might miss one cache line. 1424 */ 14254: cmpwi r6,0 1426 add r5,r3,r5 1427 beq 7f /* Always flush prefetch queue in any case */ 1428 subi r0,r6,1 1429 andc r3,r3,r0 1430 mr r4,r3 14315: dcbst 0,r4 1432 add r4,r4,r6 1433 cmplw r4,r5 1434 blt 5b 1435 sync /* Wait for all dcbst to complete on bus */ 1436 mr r4,r3 14376: icbi 0,r4 1438 add r4,r4,r6 1439 cmplw r4,r5 1440 blt 6b 14417: sync /* Wait for all icbi to complete on bus */ 1442 isync 1443 1444/* 1445 * We are done. Do not return, instead branch to second part of board 1446 * initialization, now running from RAM. 1447 */ 1448 1449 addi r0,r10,in_ram - _start + _START_OFFSET 1450 1451 /* 1452 * As IVPR is going to point RAM address, 1453 * Make sure IVOR15 has valid opcode to support debugger 1454 */ 1455 mtspr IVOR15,r0 1456 1457 /* 1458 * Re-point the IVPR at RAM 1459 */ 1460 mtspr IVPR,r10 1461 1462 mtlr r0 1463 blr /* NEVER RETURNS! */ 1464 .globl in_ram 1465in_ram: 1466 1467 /* 1468 * Relocation Function, r12 point to got2+0x8000 1469 * 1470 * Adjust got2 pointers, no need to check for 0, this code 1471 * already puts a few entries in the table. 1472 */ 1473 li r0,__got2_entries@sectoff@l 1474 la r3,GOT(_GOT2_TABLE_) 1475 lwz r11,GOT(_GOT2_TABLE_) 1476 mtctr r0 1477 sub r11,r3,r11 1478 addi r3,r3,-4 14791: lwzu r0,4(r3) 1480 cmpwi r0,0 1481 beq- 2f 1482 add r0,r0,r11 1483 stw r0,0(r3) 14842: bdnz 1b 1485 1486 /* 1487 * Now adjust the fixups and the pointers to the fixups 1488 * in case we need to move ourselves again. 1489 */ 1490 li r0,__fixup_entries@sectoff@l 1491 lwz r3,GOT(_FIXUP_TABLE_) 1492 cmpwi r0,0 1493 mtctr r0 1494 addi r3,r3,-4 1495 beq 4f 14963: lwzu r4,4(r3) 1497 lwzux r0,r4,r11 1498 cmpwi r0,0 1499 add r0,r0,r11 1500 stw r4,0(r3) 1501 beq- 5f 1502 stw r0,0(r4) 15035: bdnz 3b 15044: 1505clear_bss: 1506 /* 1507 * Now clear BSS segment 1508 */ 1509 lwz r3,GOT(__bss_start) 1510 lwz r4,GOT(__bss_end__) 1511 1512 cmplw 0,r3,r4 1513 beq 6f 1514 1515 li r0,0 15165: 1517 stw r0,0(r3) 1518 addi r3,r3,4 1519 cmplw 0,r3,r4 1520 bne 5b 15216: 1522 1523 mr r3,r9 /* Init Data pointer */ 1524 mr r4,r10 /* Destination Address */ 1525 bl board_init_r 1526 1527#ifndef CONFIG_NAND_SPL 1528 /* 1529 * Copy exception vector code to low memory 1530 * 1531 * r3: dest_addr 1532 * r7: source address, r8: end address, r9: target address 1533 */ 1534 .globl trap_init 1535trap_init: 1536 mflr r4 /* save link register */ 1537 GET_GOT 1538 lwz r7,GOT(_start_of_vectors) 1539 lwz r8,GOT(_end_of_vectors) 1540 1541 li r9,0x100 /* reset vector always at 0x100 */ 1542 1543 cmplw 0,r7,r8 1544 bgelr /* return if r7>=r8 - just in case */ 15451: 1546 lwz r0,0(r7) 1547 stw r0,0(r9) 1548 addi r7,r7,4 1549 addi r9,r9,4 1550 cmplw 0,r7,r8 1551 bne 1b 1552 1553 /* 1554 * relocate `hdlr' and `int_return' entries 1555 */ 1556 li r7,.L_CriticalInput - _start + _START_OFFSET 1557 bl trap_reloc 1558 li r7,.L_MachineCheck - _start + _START_OFFSET 1559 bl trap_reloc 1560 li r7,.L_DataStorage - _start + _START_OFFSET 1561 bl trap_reloc 1562 li r7,.L_InstStorage - _start + _START_OFFSET 1563 bl trap_reloc 1564 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1565 bl trap_reloc 1566 li r7,.L_Alignment - _start + _START_OFFSET 1567 bl trap_reloc 1568 li r7,.L_ProgramCheck - _start + _START_OFFSET 1569 bl trap_reloc 1570 li r7,.L_FPUnavailable - _start + _START_OFFSET 1571 bl trap_reloc 1572 li r7,.L_Decrementer - _start + _START_OFFSET 1573 bl trap_reloc 1574 li r7,.L_IntervalTimer - _start + _START_OFFSET 1575 li r8,_end_of_vectors - _start + _START_OFFSET 15762: 1577 bl trap_reloc 1578 addi r7,r7,0x100 /* next exception vector */ 1579 cmplw 0,r7,r8 1580 blt 2b 1581 1582 /* Update IVORs as per relocated vector table address */ 1583 li r7,0x0100 1584 mtspr IVOR0,r7 /* 0: Critical input */ 1585 li r7,0x0200 1586 mtspr IVOR1,r7 /* 1: Machine check */ 1587 li r7,0x0300 1588 mtspr IVOR2,r7 /* 2: Data storage */ 1589 li r7,0x0400 1590 mtspr IVOR3,r7 /* 3: Instruction storage */ 1591 li r7,0x0500 1592 mtspr IVOR4,r7 /* 4: External interrupt */ 1593 li r7,0x0600 1594 mtspr IVOR5,r7 /* 5: Alignment */ 1595 li r7,0x0700 1596 mtspr IVOR6,r7 /* 6: Program check */ 1597 li r7,0x0800 1598 mtspr IVOR7,r7 /* 7: floating point unavailable */ 1599 li r7,0x0900 1600 mtspr IVOR8,r7 /* 8: System call */ 1601 /* 9: Auxiliary processor unavailable(unsupported) */ 1602 li r7,0x0a00 1603 mtspr IVOR10,r7 /* 10: Decrementer */ 1604 li r7,0x0b00 1605 mtspr IVOR11,r7 /* 11: Interval timer */ 1606 li r7,0x0c00 1607 mtspr IVOR12,r7 /* 12: Watchdog timer */ 1608 li r7,0x0d00 1609 mtspr IVOR13,r7 /* 13: Data TLB error */ 1610 li r7,0x0e00 1611 mtspr IVOR14,r7 /* 14: Instruction TLB error */ 1612 li r7,0x0f00 1613 mtspr IVOR15,r7 /* 15: Debug */ 1614 1615 lis r7,0x0 1616 mtspr IVPR,r7 1617 1618 mtlr r4 /* restore link register */ 1619 blr 1620 1621.globl unlock_ram_in_cache 1622unlock_ram_in_cache: 1623 /* invalidate the INIT_RAM section */ 1624 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1625 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1626 mfspr r4,L1CFG0 1627 andi. r4,r4,0x1ff 1628 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1629 mtctr r4 16301: dcbi r0,r3 1631 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1632 bdnz 1b 1633 sync 1634 1635 /* Invalidate the TLB entries for the cache */ 1636 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1637 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1638 tlbivax 0,r3 1639 addi r3,r3,0x1000 1640 tlbivax 0,r3 1641 addi r3,r3,0x1000 1642 tlbivax 0,r3 1643 addi r3,r3,0x1000 1644 tlbivax 0,r3 1645 isync 1646 blr 1647 1648.globl flush_dcache 1649flush_dcache: 1650 mfspr r3,SPRN_L1CFG0 1651 1652 rlwinm r5,r3,9,3 /* Extract cache block size */ 1653 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1654 * are currently defined. 1655 */ 1656 li r4,32 1657 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1658 * log2(number of ways) 1659 */ 1660 slw r5,r4,r5 /* r5 = cache block size */ 1661 1662 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1663 mulli r7,r7,13 /* An 8-way cache will require 13 1664 * loads per set. 1665 */ 1666 slw r7,r7,r6 1667 1668 /* save off HID0 and set DCFA */ 1669 mfspr r8,SPRN_HID0 1670 ori r9,r8,HID0_DCFA@l 1671 mtspr SPRN_HID0,r9 1672 isync 1673 1674 lis r4,0 1675 mtctr r7 1676 16771: lwz r3,0(r4) /* Load... */ 1678 add r4,r4,r5 1679 bdnz 1b 1680 1681 msync 1682 lis r4,0 1683 mtctr r7 1684 16851: dcbf 0,r4 /* ...and flush. */ 1686 add r4,r4,r5 1687 bdnz 1b 1688 1689 /* restore HID0 */ 1690 mtspr SPRN_HID0,r8 1691 isync 1692 1693 blr 1694 1695.globl setup_ivors 1696setup_ivors: 1697 1698#include "fixed_ivor.S" 1699 blr 1700#endif /* !CONFIG_NAND_SPL */ 1701