xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/start.S (revision 0cb77bfa) 
1/*
2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003  Motorola,Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
25 *
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
28 *
29 */
30
31#include <asm-offsets.h>
32#include <config.h>
33#include <mpc85xx.h>
34#include <version.h>
35
36#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
37
38#include <ppc_asm.tmpl>
39#include <ppc_defs.h>
40
41#include <asm/cache.h>
42#include <asm/mmu.h>
43
44#undef	MSR_KERNEL
45#define MSR_KERNEL ( MSR_ME )	/* Machine Check */
46
47/*
48 * Set up GOT: Global Offset Table
49 *
50 * Use r12 to access the GOT
51 */
52	START_GOT
53	GOT_ENTRY(_GOT2_TABLE_)
54	GOT_ENTRY(_FIXUP_TABLE_)
55
56#ifndef CONFIG_NAND_SPL
57	GOT_ENTRY(_start)
58	GOT_ENTRY(_start_of_vectors)
59	GOT_ENTRY(_end_of_vectors)
60	GOT_ENTRY(transfer_to_handler)
61#endif
62
63	GOT_ENTRY(__init_end)
64	GOT_ENTRY(__bss_end__)
65	GOT_ENTRY(__bss_start)
66	END_GOT
67
68/*
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
75
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
78 *
79 */
80
81	.section .bootpg,"ax"
82	.globl _start_e500
83
84_start_e500:
85
86/* clear registers/arrays not reset by hardware */
87
88	/* L1 */
89	li	r0,2
90	mtspr	L1CSR0,r0	/* invalidate d-cache */
91	mtspr	L1CSR1,r0	/* invalidate i-cache */
92
93	mfspr	r1,DBSR
94	mtspr	DBSR,r1		/* Clear all valid bits */
95
96	/*
97	 *	Enable L1 Caches early
98	 *
99	 */
100
101#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
102	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
103	li	r2,(32 + 0)
104	mtspr	L1CSR2,r2
105#endif
106
107	/* Enable/invalidate the I-Cache */
108	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
109	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
110	mtspr	SPRN_L1CSR1,r2
1111:
112	mfspr	r3,SPRN_L1CSR1
113	and.	r1,r3,r2
114	bne	1b
115
116	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
117	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
118	mtspr	SPRN_L1CSR1,r3
119	isync
1202:
121	mfspr	r3,SPRN_L1CSR1
122	andi.	r1,r3,L1CSR1_ICE@l
123	beq	2b
124
125	/* Enable/invalidate the D-Cache */
126	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
127	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
128	mtspr	SPRN_L1CSR0,r2
1291:
130	mfspr	r3,SPRN_L1CSR0
131	and.	r1,r3,r2
132	bne	1b
133
134	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
135	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
136	mtspr	SPRN_L1CSR0,r3
137	isync
1382:
139	mfspr	r3,SPRN_L1CSR0
140	andi.	r1,r3,L1CSR0_DCE@l
141	beq	2b
142
143	/* Setup interrupt vectors */
144	lis	r1,CONFIG_SYS_MONITOR_BASE@h
145	mtspr	IVPR,r1
146
147	li	r1,0x0100
148	mtspr	IVOR0,r1	/* 0: Critical input */
149	li	r1,0x0200
150	mtspr	IVOR1,r1	/* 1: Machine check */
151	li	r1,0x0300
152	mtspr	IVOR2,r1	/* 2: Data storage */
153	li	r1,0x0400
154	mtspr	IVOR3,r1	/* 3: Instruction storage */
155	li	r1,0x0500
156	mtspr	IVOR4,r1	/* 4: External interrupt */
157	li	r1,0x0600
158	mtspr	IVOR5,r1	/* 5: Alignment */
159	li	r1,0x0700
160	mtspr	IVOR6,r1	/* 6: Program check */
161	li	r1,0x0800
162	mtspr	IVOR7,r1	/* 7: floating point unavailable */
163	li	r1,0x0900
164	mtspr	IVOR8,r1	/* 8: System call */
165	/* 9: Auxiliary processor unavailable(unsupported) */
166	li	r1,0x0a00
167	mtspr	IVOR10,r1	/* 10: Decrementer */
168	li	r1,0x0b00
169	mtspr	IVOR11,r1	/* 11: Interval timer */
170	li	r1,0x0c00
171	mtspr	IVOR12,r1	/* 12: Watchdog timer */
172	li	r1,0x0d00
173	mtspr	IVOR13,r1	/* 13: Data TLB error */
174	li	r1,0x0e00
175	mtspr	IVOR14,r1	/* 14: Instruction TLB error */
176	li	r1,0x0f00
177	mtspr	IVOR15,r1	/* 15: Debug */
178
179	/* Clear and set up some registers. */
180	li      r0,0x0000
181	lis	r1,0xffff
182	mtspr	DEC,r0			/* prevent dec exceptions */
183	mttbl	r0			/* prevent fit & wdt exceptions */
184	mttbu	r0
185	mtspr	TSR,r1			/* clear all timer exception status */
186	mtspr	TCR,r0			/* disable all */
187	mtspr	ESR,r0			/* clear exception syndrome register */
188	mtspr	MCSR,r0			/* machine check syndrome register */
189	mtxer	r0			/* clear integer exception register */
190
191#ifdef CONFIG_SYS_BOOK3E_HV
192	mtspr	MAS8,r0			/* make sure MAS8 is clear */
193#endif
194
195	/* Enable Time Base and Select Time Base Clock */
196	lis	r0,HID0_EMCP@h		/* Enable machine check */
197#if defined(CONFIG_ENABLE_36BIT_PHYS)
198	ori	r0,r0,HID0_ENMAS7@l	/* Enable MAS7 */
199#endif
200#ifndef CONFIG_E500MC
201	ori	r0,r0,HID0_TBEN@l	/* Enable Timebase */
202#endif
203	mtspr	HID0,r0
204
205#ifndef CONFIG_E500MC
206	li	r0,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
207	mfspr	r3,PVR
208	andi.	r3,r3, 0xff
209	cmpwi	r3,0x50@l	/* if we are rev 5.0 or greater set MBDD */
210	blt 1f
211	/* Set MBDD bit also */
212	ori r0, r0, HID1_MBDD@l
2131:
214	mtspr	HID1,r0
215#endif
216
217	/* Enable Branch Prediction */
218#if defined(CONFIG_BTB)
219	lis	r0,BUCSR_ENABLE@h
220	ori	r0,r0,BUCSR_ENABLE@l
221	mtspr	SPRN_BUCSR,r0
222#endif
223
224#if defined(CONFIG_SYS_INIT_DBCR)
225	lis	r1,0xffff
226	ori	r1,r1,0xffff
227	mtspr	DBSR,r1			/* Clear all status bits */
228	lis	r0,CONFIG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
229	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
230	mtspr	DBCR0,r0
231#endif
232
233#ifdef CONFIG_MPC8569
234#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
235#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
236
237	/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
238	 * use address space which is more than 12bits, and it must be done in
239	 * the 4K boot page. So we set this bit here.
240	 */
241
242	/* create a temp mapping TLB0[0] for LBCR  */
243	lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
244	ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
245
246	lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
247	ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
248
249	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
250	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
251
252	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
253						(MAS3_SX|MAS3_SW|MAS3_SR))@h
254	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
255						(MAS3_SX|MAS3_SW|MAS3_SR))@l
256
257	mtspr   MAS0,r6
258	mtspr   MAS1,r7
259	mtspr   MAS2,r8
260	mtspr   MAS3,r9
261	isync
262	msync
263	tlbwe
264
265	/* Set LBCR register */
266	lis     r4,CONFIG_SYS_LBCR_ADDR@h
267	ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
268
269	lis     r5,CONFIG_SYS_LBC_LBCR@h
270	ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
271	stw     r5,0(r4)
272	isync
273
274	/* invalidate this temp TLB */
275	lis	r4,CONFIG_SYS_LBC_ADDR@h
276	ori	r4,r4,CONFIG_SYS_LBC_ADDR@l
277	tlbivax	0,r4
278	isync
279
280#endif /* CONFIG_MPC8569 */
281
282	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
283	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
284
285#ifndef CONFIG_SYS_RAMBOOT
286	/* create a temp mapping in AS=1 to the 4M boot window */
287	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
288	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
289
290	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
291	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
292
293	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
294	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
295	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
296#else
297	/*
298	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
299	 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
300	 */
301	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
302	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
303
304	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
305	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
306
307	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
308	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
309#endif
310
311	mtspr   MAS0,r6
312	mtspr   MAS1,r7
313	mtspr   MAS2,r8
314	mtspr   MAS3,r9
315	isync
316	msync
317	tlbwe
318
319	/* create a temp mapping in AS=1 to the stack */
320	lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
321	ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
322
323	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
324	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
325
326	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
327	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
328
329#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
330    defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
331	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
332				(MAS3_SX|MAS3_SW|MAS3_SR))@h
333	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
334				(MAS3_SX|MAS3_SW|MAS3_SR))@l
335	li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
336	mtspr	MAS7,r10
337#else
338	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
339	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
340#endif
341
342	mtspr   MAS0,r6
343	mtspr   MAS1,r7
344	mtspr   MAS2,r8
345	mtspr   MAS3,r9
346	isync
347	msync
348	tlbwe
349
350	lis	r6,MSR_IS|MSR_DS@h
351	ori	r6,r6,MSR_IS|MSR_DS@l
352	lis	r7,switch_as@h
353	ori	r7,r7,switch_as@l
354
355	mtspr	SPRN_SRR0,r7
356	mtspr	SPRN_SRR1,r6
357	rfi
358
359switch_as:
360/* L1 DCache is used for initial RAM */
361
362	/* Allocate Initial RAM in data cache.
363	 */
364	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
365	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
366	mfspr	r2, L1CFG0
367	andi.	r2, r2, 0x1ff
368	/* cache size * 1024 / (2 * L1 line size) */
369	slwi	r2, r2, (10 - 1 - L1_CACHE_SHIFT)
370	mtctr	r2
371	li	r0,0
3721:
373	dcbz	r0,r3
374	dcbtls	0,r0,r3
375	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
376	bdnz	1b
377
378	/* Jump out the last 4K page and continue to 'normal' start */
379#ifdef CONFIG_SYS_RAMBOOT
380	b	_start_cont
381#else
382	/* Calculate absolute address in FLASH and jump there		*/
383	/*--------------------------------------------------------------*/
384	lis	r3,CONFIG_SYS_MONITOR_BASE@h
385	ori	r3,r3,CONFIG_SYS_MONITOR_BASE@l
386	addi	r3,r3,_start_cont - _start + _START_OFFSET
387	mtlr	r3
388	blr
389#endif
390
391	.text
392	.globl	_start
393_start:
394	.long	0x27051956		/* U-BOOT Magic Number */
395	.globl	version_string
396version_string:
397	.ascii U_BOOT_VERSION_STRING, "\0"
398
399	.align	4
400	.globl	_start_cont
401_start_cont:
402	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
403	lis	r1,CONFIG_SYS_INIT_RAM_ADDR@h
404	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
405
406	li	r0,0
407	stwu	r0,-4(r1)
408	stwu	r0,-4(r1)		/* Terminate call chain */
409
410	stwu	r1,-8(r1)		/* Save back chain and move SP */
411	lis	r0,RESET_VECTOR@h	/* Address of reset vector */
412	ori	r0,r0,RESET_VECTOR@l
413	stwu	r1,-8(r1)		/* Save back chain and move SP */
414	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
415
416	GET_GOT
417	bl	cpu_init_early_f
418
419	/* switch back to AS = 0 */
420	lis	r3,(MSR_CE|MSR_ME|MSR_DE)@h
421	ori	r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
422	mtmsr	r3
423	isync
424
425	bl	cpu_init_f
426	bl	board_init_f
427	isync
428
429	/* NOTREACHED - board_init_f() does not return */
430
431#ifndef CONFIG_NAND_SPL
432	. = EXC_OFF_SYS_RESET
433	.globl	_start_of_vectors
434_start_of_vectors:
435
436/* Critical input. */
437	CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
438
439/* Machine check */
440	MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
441
442/* Data Storage exception. */
443	STD_EXCEPTION(0x0300, DataStorage, UnknownException)
444
445/* Instruction Storage exception. */
446	STD_EXCEPTION(0x0400, InstStorage, UnknownException)
447
448/* External Interrupt exception. */
449	STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
450
451/* Alignment exception. */
452	. = 0x0600
453Alignment:
454	EXCEPTION_PROLOG(SRR0, SRR1)
455	mfspr	r4,DAR
456	stw	r4,_DAR(r21)
457	mfspr	r5,DSISR
458	stw	r5,_DSISR(r21)
459	addi	r3,r1,STACK_FRAME_OVERHEAD
460	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
461
462/* Program check exception */
463	. = 0x0700
464ProgramCheck:
465	EXCEPTION_PROLOG(SRR0, SRR1)
466	addi	r3,r1,STACK_FRAME_OVERHEAD
467	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
468		MSR_KERNEL, COPY_EE)
469
470	/* No FPU on MPC85xx.  This exception is not supposed to happen.
471	*/
472	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
473
474	. = 0x0900
475/*
476 * r0 - SYSCALL number
477 * r3-... arguments
478 */
479SystemCall:
480	addis	r11,r0,0	/* get functions table addr */
481	ori	r11,r11,0	/* Note: this code is patched in trap_init */
482	addis	r12,r0,0	/* get number of functions */
483	ori	r12,r12,0
484
485	cmplw	0,r0,r12
486	bge	1f
487
488	rlwinm	r0,r0,2,0,31	/* fn_addr = fn_tbl[r0] */
489	add	r11,r11,r0
490	lwz	r11,0(r11)
491
492	li	r20,0xd00-4	/* Get stack pointer */
493	lwz	r12,0(r20)
494	subi	r12,r12,12	/* Adjust stack pointer */
495	li	r0,0xc00+_end_back-SystemCall
496	cmplw	0,r0,r12	/* Check stack overflow */
497	bgt	1f
498	stw	r12,0(r20)
499
500	mflr	r0
501	stw	r0,0(r12)
502	mfspr	r0,SRR0
503	stw	r0,4(r12)
504	mfspr	r0,SRR1
505	stw	r0,8(r12)
506
507	li	r12,0xc00+_back-SystemCall
508	mtlr	r12
509	mtspr	SRR0,r11
510
5111:	SYNC
512	rfi
513_back:
514
515	mfmsr	r11			/* Disable interrupts */
516	li	r12,0
517	ori	r12,r12,MSR_EE
518	andc	r11,r11,r12
519	SYNC				/* Some chip revs need this... */
520	mtmsr	r11
521	SYNC
522
523	li	r12,0xd00-4		/* restore regs */
524	lwz	r12,0(r12)
525
526	lwz	r11,0(r12)
527	mtlr	r11
528	lwz	r11,4(r12)
529	mtspr	SRR0,r11
530	lwz	r11,8(r12)
531	mtspr	SRR1,r11
532
533	addi	r12,r12,12		/* Adjust stack pointer */
534	li	r20,0xd00-4
535	stw	r12,0(r20)
536
537	SYNC
538	rfi
539_end_back:
540
541	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
542	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
543	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
544
545	STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
546	STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
547
548	CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
549
550	.globl	_end_of_vectors
551_end_of_vectors:
552
553
554	. = . + (0x100 - ( . & 0xff ))	/* align for debug */
555
556/*
557 * This code finishes saving the registers to the exception frame
558 * and jumps to the appropriate handler for the exception.
559 * Register r21 is pointer into trap frame, r1 has new stack pointer.
560 */
561	.globl	transfer_to_handler
562transfer_to_handler:
563	stw	r22,_NIP(r21)
564	lis	r22,MSR_POW@h
565	andc	r23,r23,r22
566	stw	r23,_MSR(r21)
567	SAVE_GPR(7, r21)
568	SAVE_4GPRS(8, r21)
569	SAVE_8GPRS(12, r21)
570	SAVE_8GPRS(24, r21)
571
572	mflr	r23
573	andi.	r24,r23,0x3f00		/* get vector offset */
574	stw	r24,TRAP(r21)
575	li	r22,0
576	stw	r22,RESULT(r21)
577	mtspr	SPRG2,r22		/* r1 is now kernel sp */
578
579	lwz	r24,0(r23)		/* virtual address of handler */
580	lwz	r23,4(r23)		/* where to go when done */
581	mtspr	SRR0,r24
582	mtspr	SRR1,r20
583	mtlr	r23
584	SYNC
585	rfi				/* jump to handler, enable MMU */
586
587int_return:
588	mfmsr	r28		/* Disable interrupts */
589	li	r4,0
590	ori	r4,r4,MSR_EE
591	andc	r28,r28,r4
592	SYNC			/* Some chip revs need this... */
593	mtmsr	r28
594	SYNC
595	lwz	r2,_CTR(r1)
596	lwz	r0,_LINK(r1)
597	mtctr	r2
598	mtlr	r0
599	lwz	r2,_XER(r1)
600	lwz	r0,_CCR(r1)
601	mtspr	XER,r2
602	mtcrf	0xFF,r0
603	REST_10GPRS(3, r1)
604	REST_10GPRS(13, r1)
605	REST_8GPRS(23, r1)
606	REST_GPR(31, r1)
607	lwz	r2,_NIP(r1)	/* Restore environment */
608	lwz	r0,_MSR(r1)
609	mtspr	SRR0,r2
610	mtspr	SRR1,r0
611	lwz	r0,GPR0(r1)
612	lwz	r2,GPR2(r1)
613	lwz	r1,GPR1(r1)
614	SYNC
615	rfi
616
617crit_return:
618	mfmsr	r28		/* Disable interrupts */
619	li	r4,0
620	ori	r4,r4,MSR_EE
621	andc	r28,r28,r4
622	SYNC			/* Some chip revs need this... */
623	mtmsr	r28
624	SYNC
625	lwz	r2,_CTR(r1)
626	lwz	r0,_LINK(r1)
627	mtctr	r2
628	mtlr	r0
629	lwz	r2,_XER(r1)
630	lwz	r0,_CCR(r1)
631	mtspr	XER,r2
632	mtcrf	0xFF,r0
633	REST_10GPRS(3, r1)
634	REST_10GPRS(13, r1)
635	REST_8GPRS(23, r1)
636	REST_GPR(31, r1)
637	lwz	r2,_NIP(r1)	/* Restore environment */
638	lwz	r0,_MSR(r1)
639	mtspr	SPRN_CSRR0,r2
640	mtspr	SPRN_CSRR1,r0
641	lwz	r0,GPR0(r1)
642	lwz	r2,GPR2(r1)
643	lwz	r1,GPR1(r1)
644	SYNC
645	rfci
646
647mck_return:
648	mfmsr	r28		/* Disable interrupts */
649	li	r4,0
650	ori	r4,r4,MSR_EE
651	andc	r28,r28,r4
652	SYNC			/* Some chip revs need this... */
653	mtmsr	r28
654	SYNC
655	lwz	r2,_CTR(r1)
656	lwz	r0,_LINK(r1)
657	mtctr	r2
658	mtlr	r0
659	lwz	r2,_XER(r1)
660	lwz	r0,_CCR(r1)
661	mtspr	XER,r2
662	mtcrf	0xFF,r0
663	REST_10GPRS(3, r1)
664	REST_10GPRS(13, r1)
665	REST_8GPRS(23, r1)
666	REST_GPR(31, r1)
667	lwz	r2,_NIP(r1)	/* Restore environment */
668	lwz	r0,_MSR(r1)
669	mtspr	SPRN_MCSRR0,r2
670	mtspr	SPRN_MCSRR1,r0
671	lwz	r0,GPR0(r1)
672	lwz	r2,GPR2(r1)
673	lwz	r1,GPR1(r1)
674	SYNC
675	rfmci
676
677/* Cache functions.
678*/
679.globl flush_icache
680flush_icache:
681.globl invalidate_icache
682invalidate_icache:
683	mfspr	r0,L1CSR1
684	ori	r0,r0,L1CSR1_ICFI
685	msync
686	isync
687	mtspr	L1CSR1,r0
688	isync
689	blr				/* entire I cache */
690
691.globl invalidate_dcache
692invalidate_dcache:
693	mfspr	r0,L1CSR0
694	ori	r0,r0,L1CSR0_DCFI
695	msync
696	isync
697	mtspr	L1CSR0,r0
698	isync
699	blr
700
701	.globl	icache_enable
702icache_enable:
703	mflr	r8
704	bl	invalidate_icache
705	mtlr	r8
706	isync
707	mfspr	r4,L1CSR1
708	ori	r4,r4,0x0001
709	oris	r4,r4,0x0001
710	mtspr	L1CSR1,r4
711	isync
712	blr
713
714	.globl	icache_disable
715icache_disable:
716	mfspr	r0,L1CSR1
717	lis	r3,0
718	ori	r3,r3,L1CSR1_ICE
719	andc	r0,r0,r3
720	mtspr	L1CSR1,r0
721	isync
722	blr
723
724	.globl	icache_status
725icache_status:
726	mfspr	r3,L1CSR1
727	andi.	r3,r3,L1CSR1_ICE
728	blr
729
730	.globl	dcache_enable
731dcache_enable:
732	mflr	r8
733	bl	invalidate_dcache
734	mtlr	r8
735	isync
736	mfspr	r0,L1CSR0
737	ori	r0,r0,0x0001
738	oris	r0,r0,0x0001
739	msync
740	isync
741	mtspr	L1CSR0,r0
742	isync
743	blr
744
745	.globl	dcache_disable
746dcache_disable:
747	mfspr	r3,L1CSR0
748	lis	r4,0
749	ori	r4,r4,L1CSR0_DCE
750	andc	r3,r3,r4
751	mtspr	L1CSR0,r3
752	isync
753	blr
754
755	.globl	dcache_status
756dcache_status:
757	mfspr	r3,L1CSR0
758	andi.	r3,r3,L1CSR0_DCE
759	blr
760
761	.globl get_pir
762get_pir:
763	mfspr	r3,PIR
764	blr
765
766	.globl get_pvr
767get_pvr:
768	mfspr	r3,PVR
769	blr
770
771	.globl get_svr
772get_svr:
773	mfspr	r3,SVR
774	blr
775
776	.globl wr_tcr
777wr_tcr:
778	mtspr	TCR,r3
779	blr
780
781/*------------------------------------------------------------------------------- */
782/* Function:	 in8 */
783/* Description:	 Input 8 bits */
784/*------------------------------------------------------------------------------- */
785	.globl	in8
786in8:
787	lbz	r3,0x0000(r3)
788	blr
789
790/*------------------------------------------------------------------------------- */
791/* Function:	 out8 */
792/* Description:	 Output 8 bits */
793/*------------------------------------------------------------------------------- */
794	.globl	out8
795out8:
796	stb	r4,0x0000(r3)
797	sync
798	blr
799
800/*------------------------------------------------------------------------------- */
801/* Function:	 out16 */
802/* Description:	 Output 16 bits */
803/*------------------------------------------------------------------------------- */
804	.globl	out16
805out16:
806	sth	r4,0x0000(r3)
807	sync
808	blr
809
810/*------------------------------------------------------------------------------- */
811/* Function:	 out16r */
812/* Description:	 Byte reverse and output 16 bits */
813/*------------------------------------------------------------------------------- */
814	.globl	out16r
815out16r:
816	sthbrx	r4,r0,r3
817	sync
818	blr
819
820/*------------------------------------------------------------------------------- */
821/* Function:	 out32 */
822/* Description:	 Output 32 bits */
823/*------------------------------------------------------------------------------- */
824	.globl	out32
825out32:
826	stw	r4,0x0000(r3)
827	sync
828	blr
829
830/*------------------------------------------------------------------------------- */
831/* Function:	 out32r */
832/* Description:	 Byte reverse and output 32 bits */
833/*------------------------------------------------------------------------------- */
834	.globl	out32r
835out32r:
836	stwbrx	r4,r0,r3
837	sync
838	blr
839
840/*------------------------------------------------------------------------------- */
841/* Function:	 in16 */
842/* Description:	 Input 16 bits */
843/*------------------------------------------------------------------------------- */
844	.globl	in16
845in16:
846	lhz	r3,0x0000(r3)
847	blr
848
849/*------------------------------------------------------------------------------- */
850/* Function:	 in16r */
851/* Description:	 Input 16 bits and byte reverse */
852/*------------------------------------------------------------------------------- */
853	.globl	in16r
854in16r:
855	lhbrx	r3,r0,r3
856	blr
857
858/*------------------------------------------------------------------------------- */
859/* Function:	 in32 */
860/* Description:	 Input 32 bits */
861/*------------------------------------------------------------------------------- */
862	.globl	in32
863in32:
864	lwz	3,0x0000(3)
865	blr
866
867/*------------------------------------------------------------------------------- */
868/* Function:	 in32r */
869/* Description:	 Input 32 bits and byte reverse */
870/*------------------------------------------------------------------------------- */
871	.globl	in32r
872in32r:
873	lwbrx	r3,r0,r3
874	blr
875#endif  /* !CONFIG_NAND_SPL */
876
877/*------------------------------------------------------------------------------*/
878
879/*
880 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
881 */
882	.globl	write_tlb
883write_tlb:
884	mtspr	MAS0,r3
885	mtspr	MAS1,r4
886	mtspr	MAS2,r5
887	mtspr	MAS3,r6
888#ifdef CONFIG_ENABLE_36BIT_PHYS
889	mtspr	MAS7,r7
890#endif
891	li	r3,0
892#ifdef CONFIG_SYS_BOOK3E_HV
893	mtspr	MAS8,r3
894#endif
895	isync
896	tlbwe
897	msync
898	isync
899	blr
900
901/*
902 * void relocate_code (addr_sp, gd, addr_moni)
903 *
904 * This "function" does not return, instead it continues in RAM
905 * after relocating the monitor code.
906 *
907 * r3 = dest
908 * r4 = src
909 * r5 = length in bytes
910 * r6 = cachelinesize
911 */
912	.globl	relocate_code
913relocate_code:
914	mr	r1,r3		/* Set new stack pointer		*/
915	mr	r9,r4		/* Save copy of Init Data pointer	*/
916	mr	r10,r5		/* Save copy of Destination Address	*/
917
918	GET_GOT
919	mr	r3,r5				/* Destination Address	*/
920	lis	r4,CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
921	ori	r4,r4,CONFIG_SYS_MONITOR_BASE@l
922	lwz	r5,GOT(__init_end)
923	sub	r5,r5,r4
924	li	r6,CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
925
926	/*
927	 * Fix GOT pointer:
928	 *
929	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
930	 *
931	 * Offset:
932	 */
933	sub	r15,r10,r4
934
935	/* First our own GOT */
936	add	r12,r12,r15
937	/* the the one used by the C code */
938	add	r30,r30,r15
939
940	/*
941	 * Now relocate code
942	 */
943
944	cmplw	cr1,r3,r4
945	addi	r0,r5,3
946	srwi.	r0,r0,2
947	beq	cr1,4f		/* In place copy is not necessary	*/
948	beq	7f		/* Protect against 0 count		*/
949	mtctr	r0
950	bge	cr1,2f
951
952	la	r8,-4(r4)
953	la	r7,-4(r3)
9541:	lwzu	r0,4(r8)
955	stwu	r0,4(r7)
956	bdnz	1b
957	b	4f
958
9592:	slwi	r0,r0,2
960	add	r8,r4,r0
961	add	r7,r3,r0
9623:	lwzu	r0,-4(r8)
963	stwu	r0,-4(r7)
964	bdnz	3b
965
966/*
967 * Now flush the cache: note that we must start from a cache aligned
968 * address. Otherwise we might miss one cache line.
969 */
9704:	cmpwi	r6,0
971	add	r5,r3,r5
972	beq	7f		/* Always flush prefetch queue in any case */
973	subi	r0,r6,1
974	andc	r3,r3,r0
975	mr	r4,r3
9765:	dcbst	0,r4
977	add	r4,r4,r6
978	cmplw	r4,r5
979	blt	5b
980	sync			/* Wait for all dcbst to complete on bus */
981	mr	r4,r3
9826:	icbi	0,r4
983	add	r4,r4,r6
984	cmplw	r4,r5
985	blt	6b
9867:	sync			/* Wait for all icbi to complete on bus */
987	isync
988
989	/*
990	 * Re-point the IVPR at RAM
991	 */
992	mtspr	IVPR,r10
993
994/*
995 * We are done. Do not return, instead branch to second part of board
996 * initialization, now running from RAM.
997 */
998
999	addi	r0,r10,in_ram - _start + _START_OFFSET
1000	mtlr	r0
1001	blr				/* NEVER RETURNS! */
1002	.globl	in_ram
1003in_ram:
1004
1005	/*
1006	 * Relocation Function, r12 point to got2+0x8000
1007	 *
1008	 * Adjust got2 pointers, no need to check for 0, this code
1009	 * already puts a few entries in the table.
1010	 */
1011	li	r0,__got2_entries@sectoff@l
1012	la	r3,GOT(_GOT2_TABLE_)
1013	lwz	r11,GOT(_GOT2_TABLE_)
1014	mtctr	r0
1015	sub	r11,r3,r11
1016	addi	r3,r3,-4
10171:	lwzu	r0,4(r3)
1018	cmpwi	r0,0
1019	beq-	2f
1020	add	r0,r0,r11
1021	stw	r0,0(r3)
10222:	bdnz	1b
1023
1024	/*
1025	 * Now adjust the fixups and the pointers to the fixups
1026	 * in case we need to move ourselves again.
1027	 */
1028	li	r0,__fixup_entries@sectoff@l
1029	lwz	r3,GOT(_FIXUP_TABLE_)
1030	cmpwi	r0,0
1031	mtctr	r0
1032	addi	r3,r3,-4
1033	beq	4f
10343:	lwzu	r4,4(r3)
1035	lwzux	r0,r4,r11
1036	cmpwi	r0,0
1037	add	r0,r0,r11
1038	stw	r4,0(r3)
1039	beq-	5f
1040	stw	r0,0(r4)
10415:	bdnz	3b
10424:
1043clear_bss:
1044	/*
1045	 * Now clear BSS segment
1046	 */
1047	lwz	r3,GOT(__bss_start)
1048	lwz	r4,GOT(__bss_end__)
1049
1050	cmplw	0,r3,r4
1051	beq	6f
1052
1053	li	r0,0
10545:
1055	stw	r0,0(r3)
1056	addi	r3,r3,4
1057	cmplw	0,r3,r4
1058	bne	5b
10596:
1060
1061	mr	r3,r9		/* Init Data pointer		*/
1062	mr	r4,r10		/* Destination Address		*/
1063	bl	board_init_r
1064
1065#ifndef CONFIG_NAND_SPL
1066	/*
1067	 * Copy exception vector code to low memory
1068	 *
1069	 * r3: dest_addr
1070	 * r7: source address, r8: end address, r9: target address
1071	 */
1072	.globl	trap_init
1073trap_init:
1074	mflr	r4			/* save link register		*/
1075	GET_GOT
1076	lwz	r7,GOT(_start_of_vectors)
1077	lwz	r8,GOT(_end_of_vectors)
1078
1079	li	r9,0x100		/* reset vector always at 0x100 */
1080
1081	cmplw	0,r7,r8
1082	bgelr				/* return if r7>=r8 - just in case */
10831:
1084	lwz	r0,0(r7)
1085	stw	r0,0(r9)
1086	addi	r7,r7,4
1087	addi	r9,r9,4
1088	cmplw	0,r7,r8
1089	bne	1b
1090
1091	/*
1092	 * relocate `hdlr' and `int_return' entries
1093	 */
1094	li	r7,.L_CriticalInput - _start + _START_OFFSET
1095	bl	trap_reloc
1096	li	r7,.L_MachineCheck - _start + _START_OFFSET
1097	bl	trap_reloc
1098	li	r7,.L_DataStorage - _start + _START_OFFSET
1099	bl	trap_reloc
1100	li	r7,.L_InstStorage - _start + _START_OFFSET
1101	bl	trap_reloc
1102	li	r7,.L_ExtInterrupt - _start + _START_OFFSET
1103	bl	trap_reloc
1104	li	r7,.L_Alignment - _start + _START_OFFSET
1105	bl	trap_reloc
1106	li	r7,.L_ProgramCheck - _start + _START_OFFSET
1107	bl	trap_reloc
1108	li	r7,.L_FPUnavailable - _start + _START_OFFSET
1109	bl	trap_reloc
1110	li	r7,.L_Decrementer - _start + _START_OFFSET
1111	bl	trap_reloc
1112	li	r7,.L_IntervalTimer - _start + _START_OFFSET
1113	li	r8,_end_of_vectors - _start + _START_OFFSET
11142:
1115	bl	trap_reloc
1116	addi	r7,r7,0x100		/* next exception vector	*/
1117	cmplw	0,r7,r8
1118	blt	2b
1119
1120	lis	r7,0x0
1121	mtspr	IVPR,r7
1122
1123	mtlr	r4			/* restore link register	*/
1124	blr
1125
1126.globl unlock_ram_in_cache
1127unlock_ram_in_cache:
1128	/* invalidate the INIT_RAM section */
1129	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1130	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1131	mfspr	r4,L1CFG0
1132	andi.	r4,r4,0x1ff
1133	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1134	mtctr	r4
11351:	dcbi	r0,r3
1136	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
1137	bdnz	1b
1138	sync
1139
1140	/* Invalidate the TLB entries for the cache */
1141	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
1142	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1143	tlbivax	0,r3
1144	addi	r3,r3,0x1000
1145	tlbivax	0,r3
1146	addi	r3,r3,0x1000
1147	tlbivax	0,r3
1148	addi	r3,r3,0x1000
1149	tlbivax	0,r3
1150	isync
1151	blr
1152
1153.globl flush_dcache
1154flush_dcache:
1155	mfspr	r3,SPRN_L1CFG0
1156
1157	rlwinm	r5,r3,9,3	/* Extract cache block size */
1158	twlgti	r5,1		/* Only 32 and 64 byte cache blocks
1159				 * are currently defined.
1160				 */
1161	li	r4,32
1162	subfic	r6,r5,2		/* r6 = log2(1KiB / cache block size) -
1163				 *      log2(number of ways)
1164				 */
1165	slw	r5,r4,r5	/* r5 = cache block size */
1166
1167	rlwinm	r7,r3,0,0xff	/* Extract number of KiB in the cache */
1168	mulli	r7,r7,13	/* An 8-way cache will require 13
1169				 * loads per set.
1170				 */
1171	slw	r7,r7,r6
1172
1173	/* save off HID0 and set DCFA */
1174	mfspr	r8,SPRN_HID0
1175	ori	r9,r8,HID0_DCFA@l
1176	mtspr	SPRN_HID0,r9
1177	isync
1178
1179	lis	r4,0
1180	mtctr	r7
1181
11821:	lwz	r3,0(r4)	/* Load... */
1183	add	r4,r4,r5
1184	bdnz	1b
1185
1186	msync
1187	lis	r4,0
1188	mtctr	r7
1189
11901:	dcbf	0,r4		/* ...and flush. */
1191	add	r4,r4,r5
1192	bdnz	1b
1193
1194	/* restore HID0 */
1195	mtspr	SPRN_HID0,r8
1196	isync
1197
1198	blr
1199
1200.globl setup_ivors
1201setup_ivors:
1202
1203#include "fixed_ivor.S"
1204	blr
1205#endif /* !CONFIG_NAND_SPL */
1206