xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/start.S (revision 071bc923) 
1/*
2 * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003  Motorola,Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
25 *
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
28 *
29 */
30
31#include <asm-offsets.h>
32#include <config.h>
33#include <mpc85xx.h>
34#include <timestamp.h>
35#include <version.h>
36
37#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
38
39#include <ppc_asm.tmpl>
40#include <ppc_defs.h>
41
42#include <asm/cache.h>
43#include <asm/mmu.h>
44
45#ifndef	 CONFIG_IDENT_STRING
46#define	 CONFIG_IDENT_STRING ""
47#endif
48
49#undef	MSR_KERNEL
50#define MSR_KERNEL ( MSR_ME )	/* Machine Check */
51
52/*
53 * Set up GOT: Global Offset Table
54 *
55 * Use r12 to access the GOT
56 */
57	START_GOT
58	GOT_ENTRY(_GOT2_TABLE_)
59	GOT_ENTRY(_FIXUP_TABLE_)
60
61#ifndef CONFIG_NAND_SPL
62	GOT_ENTRY(_start)
63	GOT_ENTRY(_start_of_vectors)
64	GOT_ENTRY(_end_of_vectors)
65	GOT_ENTRY(transfer_to_handler)
66#endif
67
68	GOT_ENTRY(__init_end)
69	GOT_ENTRY(_end)
70	GOT_ENTRY(__bss_start)
71	END_GOT
72
73/*
74 * e500 Startup -- after reset only the last 4KB of the effective
75 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
76 * section is located at THIS LAST page and basically does three
77 * things: clear some registers, set up exception tables and
78 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
79 * continue the boot procedure.
80
81 * Once the boot rom is mapped by TLB entries we can proceed
82 * with normal startup.
83 *
84 */
85
86	.section .bootpg,"ax"
87	.globl _start_e500
88
89_start_e500:
90
91/* clear registers/arrays not reset by hardware */
92
93	/* L1 */
94	li	r0,2
95	mtspr	L1CSR0,r0	/* invalidate d-cache */
96	mtspr	L1CSR1,r0	/* invalidate i-cache */
97
98	mfspr	r1,DBSR
99	mtspr	DBSR,r1		/* Clear all valid bits */
100
101	/*
102	 *	Enable L1 Caches early
103	 *
104	 */
105
106#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
107	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
108	li	r2,(32 + 0)
109	mtspr	L1CSR2,r2
110#endif
111
112	/* Enable/invalidate the I-Cache */
113	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
114	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
115	mtspr	SPRN_L1CSR1,r2
1161:
117	mfspr	r3,SPRN_L1CSR1
118	and.	r1,r3,r2
119	bne	1b
120
121	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
122	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
123	mtspr	SPRN_L1CSR1,r3
124	isync
1252:
126	mfspr	r3,SPRN_L1CSR1
127	andi.	r1,r3,L1CSR1_ICE@l
128	beq	2b
129
130	/* Enable/invalidate the D-Cache */
131	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
132	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
133	mtspr	SPRN_L1CSR0,r2
1341:
135	mfspr	r3,SPRN_L1CSR0
136	and.	r1,r3,r2
137	bne	1b
138
139	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
140	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
141	mtspr	SPRN_L1CSR0,r3
142	isync
1432:
144	mfspr	r3,SPRN_L1CSR0
145	andi.	r1,r3,L1CSR0_DCE@l
146	beq	2b
147
148	/* Setup interrupt vectors */
149	lis	r1,CONFIG_SYS_TEXT_BASE@h
150	mtspr	IVPR,r1
151
152	li	r1,0x0100
153	mtspr	IVOR0,r1	/* 0: Critical input */
154	li	r1,0x0200
155	mtspr	IVOR1,r1	/* 1: Machine check */
156	li	r1,0x0300
157	mtspr	IVOR2,r1	/* 2: Data storage */
158	li	r1,0x0400
159	mtspr	IVOR3,r1	/* 3: Instruction storage */
160	li	r1,0x0500
161	mtspr	IVOR4,r1	/* 4: External interrupt */
162	li	r1,0x0600
163	mtspr	IVOR5,r1	/* 5: Alignment */
164	li	r1,0x0700
165	mtspr	IVOR6,r1	/* 6: Program check */
166	li	r1,0x0800
167	mtspr	IVOR7,r1	/* 7: floating point unavailable */
168	li	r1,0x0900
169	mtspr	IVOR8,r1	/* 8: System call */
170	/* 9: Auxiliary processor unavailable(unsupported) */
171	li	r1,0x0a00
172	mtspr	IVOR10,r1	/* 10: Decrementer */
173	li	r1,0x0b00
174	mtspr	IVOR11,r1	/* 11: Interval timer */
175	li	r1,0x0c00
176	mtspr	IVOR12,r1	/* 12: Watchdog timer */
177	li	r1,0x0d00
178	mtspr	IVOR13,r1	/* 13: Data TLB error */
179	li	r1,0x0e00
180	mtspr	IVOR14,r1	/* 14: Instruction TLB error */
181	li	r1,0x0f00
182	mtspr	IVOR15,r1	/* 15: Debug */
183
184	/* Clear and set up some registers. */
185	li      r0,0x0000
186	lis	r1,0xffff
187	mtspr	DEC,r0			/* prevent dec exceptions */
188	mttbl	r0			/* prevent fit & wdt exceptions */
189	mttbu	r0
190	mtspr	TSR,r1			/* clear all timer exception status */
191	mtspr	TCR,r0			/* disable all */
192	mtspr	ESR,r0			/* clear exception syndrome register */
193	mtspr	MCSR,r0			/* machine check syndrome register */
194	mtxer	r0			/* clear integer exception register */
195
196#ifdef CONFIG_SYS_BOOK3E_HV
197	mtspr	MAS8,r0			/* make sure MAS8 is clear */
198#endif
199
200	/* Enable Time Base and Select Time Base Clock */
201	lis	r0,HID0_EMCP@h		/* Enable machine check */
202#if defined(CONFIG_ENABLE_36BIT_PHYS)
203	ori	r0,r0,HID0_ENMAS7@l	/* Enable MAS7 */
204#endif
205#ifndef CONFIG_E500MC
206	ori	r0,r0,HID0_TBEN@l	/* Enable Timebase */
207#endif
208	mtspr	HID0,r0
209
210#ifndef CONFIG_E500MC
211	li	r0,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
212	mfspr	r3,PVR
213	andi.	r3,r3, 0xff
214	cmpwi	r3,0x50@l	/* if we are rev 5.0 or greater set MBDD */
215	blt 1f
216	/* Set MBDD bit also */
217	ori r0, r0, HID1_MBDD@l
2181:
219	mtspr	HID1,r0
220#endif
221
222	/* Enable Branch Prediction */
223#if defined(CONFIG_BTB)
224	lis	r0,BUCSR_ENABLE@h
225	ori	r0,r0,BUCSR_ENABLE@l
226	mtspr	SPRN_BUCSR,r0
227#endif
228
229#if defined(CONFIG_SYS_INIT_DBCR)
230	lis	r1,0xffff
231	ori	r1,r1,0xffff
232	mtspr	DBSR,r1			/* Clear all status bits */
233	lis	r0,CONFIG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
234	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
235	mtspr	DBCR0,r0
236#endif
237
238#ifdef CONFIG_MPC8569
239#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
240#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
241
242	/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
243	 * use address space which is more than 12bits, and it must be done in
244	 * the 4K boot page. So we set this bit here.
245	 */
246
247	/* create a temp mapping TLB0[0] for LBCR  */
248	lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
249	ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
250
251	lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
252	ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
253
254	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
255	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
256
257	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
258						(MAS3_SX|MAS3_SW|MAS3_SR))@h
259	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
260						(MAS3_SX|MAS3_SW|MAS3_SR))@l
261
262	mtspr   MAS0,r6
263	mtspr   MAS1,r7
264	mtspr   MAS2,r8
265	mtspr   MAS3,r9
266	isync
267	msync
268	tlbwe
269
270	/* Set LBCR register */
271	lis     r4,CONFIG_SYS_LBCR_ADDR@h
272	ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
273
274	lis     r5,CONFIG_SYS_LBC_LBCR@h
275	ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
276	stw     r5,0(r4)
277	isync
278
279	/* invalidate this temp TLB */
280	lis	r4,CONFIG_SYS_LBC_ADDR@h
281	ori	r4,r4,CONFIG_SYS_LBC_ADDR@l
282	tlbivax	0,r4
283	isync
284
285#endif /* CONFIG_MPC8569 */
286
287	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
288	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
289
290#ifndef CONFIG_SYS_RAMBOOT
291	/* create a temp mapping in AS=1 to the 4M boot window */
292	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
293	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
294
295	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
296	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
297
298	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
299	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
300	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
301#else
302	/*
303	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main
304	 * image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage.
305	 */
306	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
307	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
308
309	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h
310	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l
311
312	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
313	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
314#endif
315
316	mtspr   MAS0,r6
317	mtspr   MAS1,r7
318	mtspr   MAS2,r8
319	mtspr   MAS3,r9
320	isync
321	msync
322	tlbwe
323
324	/* create a temp mapping in AS=1 to the stack */
325	lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
326	ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
327
328	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
329	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
330
331	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
332	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
333
334#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
335    defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
336	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
337				(MAS3_SX|MAS3_SW|MAS3_SR))@h
338	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
339				(MAS3_SX|MAS3_SW|MAS3_SR))@l
340	li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
341	mtspr	MAS7,r10
342#else
343	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
344	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
345#endif
346
347	mtspr   MAS0,r6
348	mtspr   MAS1,r7
349	mtspr   MAS2,r8
350	mtspr   MAS3,r9
351	isync
352	msync
353	tlbwe
354
355	lis	r6,MSR_IS|MSR_DS@h
356	ori	r6,r6,MSR_IS|MSR_DS@l
357	lis	r7,switch_as@h
358	ori	r7,r7,switch_as@l
359
360	mtspr	SPRN_SRR0,r7
361	mtspr	SPRN_SRR1,r6
362	rfi
363
364switch_as:
365/* L1 DCache is used for initial RAM */
366
367	/* Allocate Initial RAM in data cache.
368	 */
369	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
370	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
371	mfspr	r2, L1CFG0
372	andi.	r2, r2, 0x1ff
373	/* cache size * 1024 / (2 * L1 line size) */
374	slwi	r2, r2, (10 - 1 - L1_CACHE_SHIFT)
375	mtctr	r2
376	li	r0,0
3771:
378	dcbz	r0,r3
379	dcbtls	0,r0,r3
380	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
381	bdnz	1b
382
383	/* Jump out the last 4K page and continue to 'normal' start */
384#ifdef CONFIG_SYS_RAMBOOT
385	b	_start_cont
386#else
387	/* Calculate absolute address in FLASH and jump there		*/
388	/*--------------------------------------------------------------*/
389	lis	r3,CONFIG_SYS_MONITOR_BASE@h
390	ori	r3,r3,CONFIG_SYS_MONITOR_BASE@l
391	addi	r3,r3,_start_cont - _start + _START_OFFSET
392	mtlr	r3
393	blr
394#endif
395
396	.text
397	.globl	_start
398_start:
399	.long	0x27051956		/* U-BOOT Magic Number */
400	.globl	version_string
401version_string:
402	.ascii U_BOOT_VERSION
403	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
404	.ascii CONFIG_IDENT_STRING, "\0"
405
406	.align	4
407	.globl	_start_cont
408_start_cont:
409	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
410	lis	r1,CONFIG_SYS_INIT_RAM_ADDR@h
411	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
412
413	li	r0,0
414	stwu	r0,-4(r1)
415	stwu	r0,-4(r1)		/* Terminate call chain */
416
417	stwu	r1,-8(r1)		/* Save back chain and move SP */
418	lis	r0,RESET_VECTOR@h	/* Address of reset vector */
419	ori	r0,r0,RESET_VECTOR@l
420	stwu	r1,-8(r1)		/* Save back chain and move SP */
421	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
422
423	GET_GOT
424	bl	cpu_init_early_f
425
426	/* switch back to AS = 0 */
427	lis	r3,(MSR_CE|MSR_ME|MSR_DE)@h
428	ori	r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
429	mtmsr	r3
430	isync
431
432	bl	cpu_init_f
433	bl	board_init_f
434	isync
435
436	/* NOTREACHED - board_init_f() does not return */
437
438#ifndef CONFIG_NAND_SPL
439	. = EXC_OFF_SYS_RESET
440	.globl	_start_of_vectors
441_start_of_vectors:
442
443/* Critical input. */
444	CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
445
446/* Machine check */
447	MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
448
449/* Data Storage exception. */
450	STD_EXCEPTION(0x0300, DataStorage, UnknownException)
451
452/* Instruction Storage exception. */
453	STD_EXCEPTION(0x0400, InstStorage, UnknownException)
454
455/* External Interrupt exception. */
456	STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
457
458/* Alignment exception. */
459	. = 0x0600
460Alignment:
461	EXCEPTION_PROLOG(SRR0, SRR1)
462	mfspr	r4,DAR
463	stw	r4,_DAR(r21)
464	mfspr	r5,DSISR
465	stw	r5,_DSISR(r21)
466	addi	r3,r1,STACK_FRAME_OVERHEAD
467	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
468
469/* Program check exception */
470	. = 0x0700
471ProgramCheck:
472	EXCEPTION_PROLOG(SRR0, SRR1)
473	addi	r3,r1,STACK_FRAME_OVERHEAD
474	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
475		MSR_KERNEL, COPY_EE)
476
477	/* No FPU on MPC85xx.  This exception is not supposed to happen.
478	*/
479	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
480
481	. = 0x0900
482/*
483 * r0 - SYSCALL number
484 * r3-... arguments
485 */
486SystemCall:
487	addis	r11,r0,0	/* get functions table addr */
488	ori	r11,r11,0	/* Note: this code is patched in trap_init */
489	addis	r12,r0,0	/* get number of functions */
490	ori	r12,r12,0
491
492	cmplw	0,r0,r12
493	bge	1f
494
495	rlwinm	r0,r0,2,0,31	/* fn_addr = fn_tbl[r0] */
496	add	r11,r11,r0
497	lwz	r11,0(r11)
498
499	li	r20,0xd00-4	/* Get stack pointer */
500	lwz	r12,0(r20)
501	subi	r12,r12,12	/* Adjust stack pointer */
502	li	r0,0xc00+_end_back-SystemCall
503	cmplw	0,r0,r12	/* Check stack overflow */
504	bgt	1f
505	stw	r12,0(r20)
506
507	mflr	r0
508	stw	r0,0(r12)
509	mfspr	r0,SRR0
510	stw	r0,4(r12)
511	mfspr	r0,SRR1
512	stw	r0,8(r12)
513
514	li	r12,0xc00+_back-SystemCall
515	mtlr	r12
516	mtspr	SRR0,r11
517
5181:	SYNC
519	rfi
520_back:
521
522	mfmsr	r11			/* Disable interrupts */
523	li	r12,0
524	ori	r12,r12,MSR_EE
525	andc	r11,r11,r12
526	SYNC				/* Some chip revs need this... */
527	mtmsr	r11
528	SYNC
529
530	li	r12,0xd00-4		/* restore regs */
531	lwz	r12,0(r12)
532
533	lwz	r11,0(r12)
534	mtlr	r11
535	lwz	r11,4(r12)
536	mtspr	SRR0,r11
537	lwz	r11,8(r12)
538	mtspr	SRR1,r11
539
540	addi	r12,r12,12		/* Adjust stack pointer */
541	li	r20,0xd00-4
542	stw	r12,0(r20)
543
544	SYNC
545	rfi
546_end_back:
547
548	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
549	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
550	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
551
552	STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
553	STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
554
555	CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
556
557	.globl	_end_of_vectors
558_end_of_vectors:
559
560
561	. = . + (0x100 - ( . & 0xff ))	/* align for debug */
562
563/*
564 * This code finishes saving the registers to the exception frame
565 * and jumps to the appropriate handler for the exception.
566 * Register r21 is pointer into trap frame, r1 has new stack pointer.
567 */
568	.globl	transfer_to_handler
569transfer_to_handler:
570	stw	r22,_NIP(r21)
571	lis	r22,MSR_POW@h
572	andc	r23,r23,r22
573	stw	r23,_MSR(r21)
574	SAVE_GPR(7, r21)
575	SAVE_4GPRS(8, r21)
576	SAVE_8GPRS(12, r21)
577	SAVE_8GPRS(24, r21)
578
579	mflr	r23
580	andi.	r24,r23,0x3f00		/* get vector offset */
581	stw	r24,TRAP(r21)
582	li	r22,0
583	stw	r22,RESULT(r21)
584	mtspr	SPRG2,r22		/* r1 is now kernel sp */
585
586	lwz	r24,0(r23)		/* virtual address of handler */
587	lwz	r23,4(r23)		/* where to go when done */
588	mtspr	SRR0,r24
589	mtspr	SRR1,r20
590	mtlr	r23
591	SYNC
592	rfi				/* jump to handler, enable MMU */
593
594int_return:
595	mfmsr	r28		/* Disable interrupts */
596	li	r4,0
597	ori	r4,r4,MSR_EE
598	andc	r28,r28,r4
599	SYNC			/* Some chip revs need this... */
600	mtmsr	r28
601	SYNC
602	lwz	r2,_CTR(r1)
603	lwz	r0,_LINK(r1)
604	mtctr	r2
605	mtlr	r0
606	lwz	r2,_XER(r1)
607	lwz	r0,_CCR(r1)
608	mtspr	XER,r2
609	mtcrf	0xFF,r0
610	REST_10GPRS(3, r1)
611	REST_10GPRS(13, r1)
612	REST_8GPRS(23, r1)
613	REST_GPR(31, r1)
614	lwz	r2,_NIP(r1)	/* Restore environment */
615	lwz	r0,_MSR(r1)
616	mtspr	SRR0,r2
617	mtspr	SRR1,r0
618	lwz	r0,GPR0(r1)
619	lwz	r2,GPR2(r1)
620	lwz	r1,GPR1(r1)
621	SYNC
622	rfi
623
624crit_return:
625	mfmsr	r28		/* Disable interrupts */
626	li	r4,0
627	ori	r4,r4,MSR_EE
628	andc	r28,r28,r4
629	SYNC			/* Some chip revs need this... */
630	mtmsr	r28
631	SYNC
632	lwz	r2,_CTR(r1)
633	lwz	r0,_LINK(r1)
634	mtctr	r2
635	mtlr	r0
636	lwz	r2,_XER(r1)
637	lwz	r0,_CCR(r1)
638	mtspr	XER,r2
639	mtcrf	0xFF,r0
640	REST_10GPRS(3, r1)
641	REST_10GPRS(13, r1)
642	REST_8GPRS(23, r1)
643	REST_GPR(31, r1)
644	lwz	r2,_NIP(r1)	/* Restore environment */
645	lwz	r0,_MSR(r1)
646	mtspr	SPRN_CSRR0,r2
647	mtspr	SPRN_CSRR1,r0
648	lwz	r0,GPR0(r1)
649	lwz	r2,GPR2(r1)
650	lwz	r1,GPR1(r1)
651	SYNC
652	rfci
653
654mck_return:
655	mfmsr	r28		/* Disable interrupts */
656	li	r4,0
657	ori	r4,r4,MSR_EE
658	andc	r28,r28,r4
659	SYNC			/* Some chip revs need this... */
660	mtmsr	r28
661	SYNC
662	lwz	r2,_CTR(r1)
663	lwz	r0,_LINK(r1)
664	mtctr	r2
665	mtlr	r0
666	lwz	r2,_XER(r1)
667	lwz	r0,_CCR(r1)
668	mtspr	XER,r2
669	mtcrf	0xFF,r0
670	REST_10GPRS(3, r1)
671	REST_10GPRS(13, r1)
672	REST_8GPRS(23, r1)
673	REST_GPR(31, r1)
674	lwz	r2,_NIP(r1)	/* Restore environment */
675	lwz	r0,_MSR(r1)
676	mtspr	SPRN_MCSRR0,r2
677	mtspr	SPRN_MCSRR1,r0
678	lwz	r0,GPR0(r1)
679	lwz	r2,GPR2(r1)
680	lwz	r1,GPR1(r1)
681	SYNC
682	rfmci
683
684/* Cache functions.
685*/
686.globl invalidate_icache
687invalidate_icache:
688	mfspr	r0,L1CSR1
689	ori	r0,r0,L1CSR1_ICFI
690	msync
691	isync
692	mtspr	L1CSR1,r0
693	isync
694	blr				/* entire I cache */
695
696.globl invalidate_dcache
697invalidate_dcache:
698	mfspr	r0,L1CSR0
699	ori	r0,r0,L1CSR0_DCFI
700	msync
701	isync
702	mtspr	L1CSR0,r0
703	isync
704	blr
705
706	.globl	icache_enable
707icache_enable:
708	mflr	r8
709	bl	invalidate_icache
710	mtlr	r8
711	isync
712	mfspr	r4,L1CSR1
713	ori	r4,r4,0x0001
714	oris	r4,r4,0x0001
715	mtspr	L1CSR1,r4
716	isync
717	blr
718
719	.globl	icache_disable
720icache_disable:
721	mfspr	r0,L1CSR1
722	lis	r3,0
723	ori	r3,r3,L1CSR1_ICE
724	andc	r0,r0,r3
725	mtspr	L1CSR1,r0
726	isync
727	blr
728
729	.globl	icache_status
730icache_status:
731	mfspr	r3,L1CSR1
732	andi.	r3,r3,L1CSR1_ICE
733	blr
734
735	.globl	dcache_enable
736dcache_enable:
737	mflr	r8
738	bl	invalidate_dcache
739	mtlr	r8
740	isync
741	mfspr	r0,L1CSR0
742	ori	r0,r0,0x0001
743	oris	r0,r0,0x0001
744	msync
745	isync
746	mtspr	L1CSR0,r0
747	isync
748	blr
749
750	.globl	dcache_disable
751dcache_disable:
752	mfspr	r3,L1CSR0
753	lis	r4,0
754	ori	r4,r4,L1CSR0_DCE
755	andc	r3,r3,r4
756	mtspr	L1CSR0,r0
757	isync
758	blr
759
760	.globl	dcache_status
761dcache_status:
762	mfspr	r3,L1CSR0
763	andi.	r3,r3,L1CSR0_DCE
764	blr
765
766	.globl get_pir
767get_pir:
768	mfspr	r3,PIR
769	blr
770
771	.globl get_pvr
772get_pvr:
773	mfspr	r3,PVR
774	blr
775
776	.globl get_svr
777get_svr:
778	mfspr	r3,SVR
779	blr
780
781	.globl wr_tcr
782wr_tcr:
783	mtspr	TCR,r3
784	blr
785
786/*------------------------------------------------------------------------------- */
787/* Function:	 in8 */
788/* Description:	 Input 8 bits */
789/*------------------------------------------------------------------------------- */
790	.globl	in8
791in8:
792	lbz	r3,0x0000(r3)
793	blr
794
795/*------------------------------------------------------------------------------- */
796/* Function:	 out8 */
797/* Description:	 Output 8 bits */
798/*------------------------------------------------------------------------------- */
799	.globl	out8
800out8:
801	stb	r4,0x0000(r3)
802	sync
803	blr
804
805/*------------------------------------------------------------------------------- */
806/* Function:	 out16 */
807/* Description:	 Output 16 bits */
808/*------------------------------------------------------------------------------- */
809	.globl	out16
810out16:
811	sth	r4,0x0000(r3)
812	sync
813	blr
814
815/*------------------------------------------------------------------------------- */
816/* Function:	 out16r */
817/* Description:	 Byte reverse and output 16 bits */
818/*------------------------------------------------------------------------------- */
819	.globl	out16r
820out16r:
821	sthbrx	r4,r0,r3
822	sync
823	blr
824
825/*------------------------------------------------------------------------------- */
826/* Function:	 out32 */
827/* Description:	 Output 32 bits */
828/*------------------------------------------------------------------------------- */
829	.globl	out32
830out32:
831	stw	r4,0x0000(r3)
832	sync
833	blr
834
835/*------------------------------------------------------------------------------- */
836/* Function:	 out32r */
837/* Description:	 Byte reverse and output 32 bits */
838/*------------------------------------------------------------------------------- */
839	.globl	out32r
840out32r:
841	stwbrx	r4,r0,r3
842	sync
843	blr
844
845/*------------------------------------------------------------------------------- */
846/* Function:	 in16 */
847/* Description:	 Input 16 bits */
848/*------------------------------------------------------------------------------- */
849	.globl	in16
850in16:
851	lhz	r3,0x0000(r3)
852	blr
853
854/*------------------------------------------------------------------------------- */
855/* Function:	 in16r */
856/* Description:	 Input 16 bits and byte reverse */
857/*------------------------------------------------------------------------------- */
858	.globl	in16r
859in16r:
860	lhbrx	r3,r0,r3
861	blr
862
863/*------------------------------------------------------------------------------- */
864/* Function:	 in32 */
865/* Description:	 Input 32 bits */
866/*------------------------------------------------------------------------------- */
867	.globl	in32
868in32:
869	lwz	3,0x0000(3)
870	blr
871
872/*------------------------------------------------------------------------------- */
873/* Function:	 in32r */
874/* Description:	 Input 32 bits and byte reverse */
875/*------------------------------------------------------------------------------- */
876	.globl	in32r
877in32r:
878	lwbrx	r3,r0,r3
879	blr
880#endif  /* !CONFIG_NAND_SPL */
881
882/*------------------------------------------------------------------------------*/
883
884/*
885 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
886 */
887	.globl	write_tlb
888write_tlb:
889	mtspr	MAS0,r3
890	mtspr	MAS1,r4
891	mtspr	MAS2,r5
892	mtspr	MAS3,r6
893#ifdef CONFIG_ENABLE_36BIT_PHYS
894	mtspr	MAS7,r7
895#endif
896	li	r3,0
897#ifdef CONFIG_SYS_BOOK3E_HV
898	mtspr	MAS8,r3
899#endif
900	isync
901	tlbwe
902	msync
903	isync
904	blr
905
906/*
907 * void relocate_code (addr_sp, gd, addr_moni)
908 *
909 * This "function" does not return, instead it continues in RAM
910 * after relocating the monitor code.
911 *
912 * r3 = dest
913 * r4 = src
914 * r5 = length in bytes
915 * r6 = cachelinesize
916 */
917	.globl	relocate_code
918relocate_code:
919	mr	r1,r3		/* Set new stack pointer		*/
920	mr	r9,r4		/* Save copy of Init Data pointer	*/
921	mr	r10,r5		/* Save copy of Destination Address	*/
922
923	GET_GOT
924	mr	r3,r5				/* Destination Address	*/
925	lis	r4,CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
926	ori	r4,r4,CONFIG_SYS_MONITOR_BASE@l
927	lwz	r5,GOT(__init_end)
928	sub	r5,r5,r4
929	li	r6,CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
930
931	/*
932	 * Fix GOT pointer:
933	 *
934	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
935	 *
936	 * Offset:
937	 */
938	sub	r15,r10,r4
939
940	/* First our own GOT */
941	add	r12,r12,r15
942	/* the the one used by the C code */
943	add	r30,r30,r15
944
945	/*
946	 * Now relocate code
947	 */
948
949	cmplw	cr1,r3,r4
950	addi	r0,r5,3
951	srwi.	r0,r0,2
952	beq	cr1,4f		/* In place copy is not necessary	*/
953	beq	7f		/* Protect against 0 count		*/
954	mtctr	r0
955	bge	cr1,2f
956
957	la	r8,-4(r4)
958	la	r7,-4(r3)
9591:	lwzu	r0,4(r8)
960	stwu	r0,4(r7)
961	bdnz	1b
962	b	4f
963
9642:	slwi	r0,r0,2
965	add	r8,r4,r0
966	add	r7,r3,r0
9673:	lwzu	r0,-4(r8)
968	stwu	r0,-4(r7)
969	bdnz	3b
970
971/*
972 * Now flush the cache: note that we must start from a cache aligned
973 * address. Otherwise we might miss one cache line.
974 */
9754:	cmpwi	r6,0
976	add	r5,r3,r5
977	beq	7f		/* Always flush prefetch queue in any case */
978	subi	r0,r6,1
979	andc	r3,r3,r0
980	mr	r4,r3
9815:	dcbst	0,r4
982	add	r4,r4,r6
983	cmplw	r4,r5
984	blt	5b
985	sync			/* Wait for all dcbst to complete on bus */
986	mr	r4,r3
9876:	icbi	0,r4
988	add	r4,r4,r6
989	cmplw	r4,r5
990	blt	6b
9917:	sync			/* Wait for all icbi to complete on bus */
992	isync
993
994	/*
995	 * Re-point the IVPR at RAM
996	 */
997	mtspr	IVPR,r10
998
999/*
1000 * We are done. Do not return, instead branch to second part of board
1001 * initialization, now running from RAM.
1002 */
1003
1004	addi	r0,r10,in_ram - _start + _START_OFFSET
1005	mtlr	r0
1006	blr				/* NEVER RETURNS! */
1007	.globl	in_ram
1008in_ram:
1009
1010	/*
1011	 * Relocation Function, r12 point to got2+0x8000
1012	 *
1013	 * Adjust got2 pointers, no need to check for 0, this code
1014	 * already puts a few entries in the table.
1015	 */
1016	li	r0,__got2_entries@sectoff@l
1017	la	r3,GOT(_GOT2_TABLE_)
1018	lwz	r11,GOT(_GOT2_TABLE_)
1019	mtctr	r0
1020	sub	r11,r3,r11
1021	addi	r3,r3,-4
10221:	lwzu	r0,4(r3)
1023	cmpwi	r0,0
1024	beq-	2f
1025	add	r0,r0,r11
1026	stw	r0,0(r3)
10272:	bdnz	1b
1028
1029	/*
1030	 * Now adjust the fixups and the pointers to the fixups
1031	 * in case we need to move ourselves again.
1032	 */
1033	li	r0,__fixup_entries@sectoff@l
1034	lwz	r3,GOT(_FIXUP_TABLE_)
1035	cmpwi	r0,0
1036	mtctr	r0
1037	addi	r3,r3,-4
1038	beq	4f
10393:	lwzu	r4,4(r3)
1040	lwzux	r0,r4,r11
1041	cmpwi	r0,0
1042	add	r0,r0,r11
1043	stw	r10,0(r3)
1044	beq-	5f
1045	stw	r0,0(r4)
10465:	bdnz	3b
10474:
1048clear_bss:
1049	/*
1050	 * Now clear BSS segment
1051	 */
1052	lwz	r3,GOT(__bss_start)
1053	lwz	r4,GOT(_end)
1054
1055	cmplw	0,r3,r4
1056	beq	6f
1057
1058	li	r0,0
10595:
1060	stw	r0,0(r3)
1061	addi	r3,r3,4
1062	cmplw	0,r3,r4
1063	bne	5b
10646:
1065
1066	mr	r3,r9		/* Init Data pointer		*/
1067	mr	r4,r10		/* Destination Address		*/
1068	bl	board_init_r
1069
1070#ifndef CONFIG_NAND_SPL
1071	/*
1072	 * Copy exception vector code to low memory
1073	 *
1074	 * r3: dest_addr
1075	 * r7: source address, r8: end address, r9: target address
1076	 */
1077	.globl	trap_init
1078trap_init:
1079	mflr	r4			/* save link register		*/
1080	GET_GOT
1081	lwz	r7,GOT(_start_of_vectors)
1082	lwz	r8,GOT(_end_of_vectors)
1083
1084	li	r9,0x100		/* reset vector always at 0x100 */
1085
1086	cmplw	0,r7,r8
1087	bgelr				/* return if r7>=r8 - just in case */
10881:
1089	lwz	r0,0(r7)
1090	stw	r0,0(r9)
1091	addi	r7,r7,4
1092	addi	r9,r9,4
1093	cmplw	0,r7,r8
1094	bne	1b
1095
1096	/*
1097	 * relocate `hdlr' and `int_return' entries
1098	 */
1099	li	r7,.L_CriticalInput - _start + _START_OFFSET
1100	bl	trap_reloc
1101	li	r7,.L_MachineCheck - _start + _START_OFFSET
1102	bl	trap_reloc
1103	li	r7,.L_DataStorage - _start + _START_OFFSET
1104	bl	trap_reloc
1105	li	r7,.L_InstStorage - _start + _START_OFFSET
1106	bl	trap_reloc
1107	li	r7,.L_ExtInterrupt - _start + _START_OFFSET
1108	bl	trap_reloc
1109	li	r7,.L_Alignment - _start + _START_OFFSET
1110	bl	trap_reloc
1111	li	r7,.L_ProgramCheck - _start + _START_OFFSET
1112	bl	trap_reloc
1113	li	r7,.L_FPUnavailable - _start + _START_OFFSET
1114	bl	trap_reloc
1115	li	r7,.L_Decrementer - _start + _START_OFFSET
1116	bl	trap_reloc
1117	li	r7,.L_IntervalTimer - _start + _START_OFFSET
1118	li	r8,_end_of_vectors - _start + _START_OFFSET
11192:
1120	bl	trap_reloc
1121	addi	r7,r7,0x100		/* next exception vector	*/
1122	cmplw	0,r7,r8
1123	blt	2b
1124
1125	lis	r7,0x0
1126	mtspr	IVPR,r7
1127
1128	mtlr	r4			/* restore link register	*/
1129	blr
1130
1131.globl unlock_ram_in_cache
1132unlock_ram_in_cache:
1133	/* invalidate the INIT_RAM section */
1134	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1135	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1136	mfspr	r4,L1CFG0
1137	andi.	r4,r4,0x1ff
1138	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1139	mtctr	r4
11401:	dcbi	r0,r3
1141	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
1142	bdnz	1b
1143	sync
1144
1145	/* Invalidate the TLB entries for the cache */
1146	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
1147	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1148	tlbivax	0,r3
1149	addi	r3,r3,0x1000
1150	tlbivax	0,r3
1151	addi	r3,r3,0x1000
1152	tlbivax	0,r3
1153	addi	r3,r3,0x1000
1154	tlbivax	0,r3
1155	isync
1156	blr
1157
1158.globl flush_dcache
1159flush_dcache:
1160	mfspr	r3,SPRN_L1CFG0
1161
1162	rlwinm	r5,r3,9,3	/* Extract cache block size */
1163	twlgti	r5,1		/* Only 32 and 64 byte cache blocks
1164				 * are currently defined.
1165				 */
1166	li	r4,32
1167	subfic	r6,r5,2		/* r6 = log2(1KiB / cache block size) -
1168				 *      log2(number of ways)
1169				 */
1170	slw	r5,r4,r5	/* r5 = cache block size */
1171
1172	rlwinm	r7,r3,0,0xff	/* Extract number of KiB in the cache */
1173	mulli	r7,r7,13	/* An 8-way cache will require 13
1174				 * loads per set.
1175				 */
1176	slw	r7,r7,r6
1177
1178	/* save off HID0 and set DCFA */
1179	mfspr	r8,SPRN_HID0
1180	ori	r9,r8,HID0_DCFA@l
1181	mtspr	SPRN_HID0,r9
1182	isync
1183
1184	lis	r4,0
1185	mtctr	r7
1186
11871:	lwz	r3,0(r4)	/* Load... */
1188	add	r4,r4,r5
1189	bdnz	1b
1190
1191	msync
1192	lis	r4,0
1193	mtctr	r7
1194
11951:	dcbf	0,r4		/* ...and flush. */
1196	add	r4,r4,r5
1197	bdnz	1b
1198
1199	/* restore HID0 */
1200	mtspr	SPRN_HID0,r8
1201	isync
1202
1203	blr
1204
1205.globl setup_ivors
1206setup_ivors:
1207
1208#include "fixed_ivor.S"
1209	blr
1210#endif /* !CONFIG_NAND_SPL */
1211