1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* --------------------------------------------------------------- */ 22 23 void get_sys_info(sys_info_t *sys_info) 24 { 25 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 26 #ifdef CONFIG_FSL_IFC 27 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 28 u32 ccr; 29 #endif 30 #ifdef CONFIG_FSL_CORENET 31 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 32 unsigned int cpu; 33 34 const u8 core_cplx_PLL[16] = { 35 [ 0] = 0, /* CC1 PPL / 1 */ 36 [ 1] = 0, /* CC1 PPL / 2 */ 37 [ 2] = 0, /* CC1 PPL / 4 */ 38 [ 4] = 1, /* CC2 PPL / 1 */ 39 [ 5] = 1, /* CC2 PPL / 2 */ 40 [ 6] = 1, /* CC2 PPL / 4 */ 41 [ 8] = 2, /* CC3 PPL / 1 */ 42 [ 9] = 2, /* CC3 PPL / 2 */ 43 [10] = 2, /* CC3 PPL / 4 */ 44 [12] = 3, /* CC4 PPL / 1 */ 45 [13] = 3, /* CC4 PPL / 2 */ 46 [14] = 3, /* CC4 PPL / 4 */ 47 }; 48 49 const u8 core_cplx_pll_div[16] = { 50 [ 0] = 1, /* CC1 PPL / 1 */ 51 [ 1] = 2, /* CC1 PPL / 2 */ 52 [ 2] = 4, /* CC1 PPL / 4 */ 53 [ 4] = 1, /* CC2 PPL / 1 */ 54 [ 5] = 2, /* CC2 PPL / 2 */ 55 [ 6] = 4, /* CC2 PPL / 4 */ 56 [ 8] = 1, /* CC3 PPL / 1 */ 57 [ 9] = 2, /* CC3 PPL / 2 */ 58 [10] = 4, /* CC3 PPL / 4 */ 59 [12] = 1, /* CC4 PPL / 1 */ 60 [13] = 2, /* CC4 PPL / 2 */ 61 [14] = 4, /* CC4 PPL / 4 */ 62 }; 63 uint i, freq_cc_pll[6], rcw_tmp; 64 uint ratio[6]; 65 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 66 uint mem_pll_rat; 67 68 sys_info->freq_systembus = sysclk; 69 #ifdef CONFIG_DDR_CLK_FREQ 70 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 71 #else 72 sys_info->freq_ddrbus = sysclk; 73 #endif 74 75 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 76 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 77 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 78 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 79 if (mem_pll_rat > 2) 80 sys_info->freq_ddrbus *= mem_pll_rat; 81 else 82 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 83 84 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 85 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 86 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 87 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 88 ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f; 89 ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f; 90 for (i = 0; i < 6; i++) { 91 if (ratio[i] > 4) 92 freq_cc_pll[i] = sysclk * ratio[i]; 93 else 94 freq_cc_pll[i] = sys_info->freq_systembus * ratio[i]; 95 } 96 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 97 /* 98 * Each cluster has up to 4 cores, sharing the same PLL selection. 99 * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are 100 * cluster group A, feeding cores on cluster 1 and cluster 2. 101 * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 102 * and cluster 4 if existing. 103 */ 104 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 105 int cluster = fsl_qoriq_core_to_cluster(cpu); 106 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 107 & 0xf; 108 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 109 if (cplx_pll > 3) 110 printf("Unsupported architecture configuration" 111 " in function %s\n", __func__); 112 cplx_pll += (cluster / 2) * 3; 113 sys_info->freq_processor[cpu] = 114 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 115 } 116 #ifdef CONFIG_PPC_B4860 117 #define FM1_CLK_SEL 0xe0000000 118 #define FM1_CLK_SHIFT 29 119 #else 120 #define PME_CLK_SEL 0xe0000000 121 #define PME_CLK_SHIFT 29 122 #define FM1_CLK_SEL 0x1c000000 123 #define FM1_CLK_SHIFT 26 124 #endif 125 rcw_tmp = in_be32(&gur->rcwsr[7]); 126 127 #ifdef CONFIG_SYS_DPAA_PME 128 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 129 case 1: 130 sys_info->freq_pme = freq_cc_pll[0]; 131 break; 132 case 2: 133 sys_info->freq_pme = freq_cc_pll[0] / 2; 134 break; 135 case 3: 136 sys_info->freq_pme = freq_cc_pll[0] / 3; 137 break; 138 case 4: 139 sys_info->freq_pme = freq_cc_pll[0] / 4; 140 break; 141 case 6: 142 sys_info->freq_pme = freq_cc_pll[1] / 2; 143 break; 144 case 7: 145 sys_info->freq_pme = freq_cc_pll[1] / 3; 146 break; 147 default: 148 printf("Error: Unknown PME clock select!\n"); 149 case 0: 150 sys_info->freq_pme = sys_info->freq_systembus / 2; 151 break; 152 153 } 154 #endif 155 156 #ifdef CONFIG_SYS_DPAA_QBMAN 157 sys_info->freq_qman = sys_info->freq_systembus / 2; 158 #endif 159 160 #ifdef CONFIG_SYS_DPAA_FMAN 161 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 162 case 1: 163 sys_info->freq_fman[0] = freq_cc_pll[3]; 164 break; 165 case 2: 166 sys_info->freq_fman[0] = freq_cc_pll[3] / 2; 167 break; 168 case 3: 169 sys_info->freq_fman[0] = freq_cc_pll[3] / 3; 170 break; 171 case 4: 172 sys_info->freq_fman[0] = freq_cc_pll[3] / 4; 173 break; 174 case 5: 175 sys_info->freq_fman[0] = sys_info->freq_systembus; 176 break; 177 case 6: 178 sys_info->freq_fman[0] = freq_cc_pll[4] / 2; 179 break; 180 case 7: 181 sys_info->freq_fman[0] = freq_cc_pll[4] / 3; 182 break; 183 default: 184 printf("Error: Unknown FMan1 clock select!\n"); 185 case 0: 186 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 187 break; 188 } 189 #if (CONFIG_SYS_NUM_FMAN) == 2 190 #define FM2_CLK_SEL 0x00000038 191 #define FM2_CLK_SHIFT 3 192 rcw_tmp = in_be32(&gur->rcwsr[15]); 193 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 194 case 1: 195 sys_info->freq_fman[1] = freq_cc_pll[4]; 196 break; 197 case 2: 198 sys_info->freq_fman[1] = freq_cc_pll[4] / 2; 199 break; 200 case 3: 201 sys_info->freq_fman[1] = freq_cc_pll[4] / 3; 202 break; 203 case 4: 204 sys_info->freq_fman[1] = freq_cc_pll[4] / 4; 205 break; 206 case 6: 207 sys_info->freq_fman[1] = freq_cc_pll[3] / 2; 208 break; 209 case 7: 210 sys_info->freq_fman[1] = freq_cc_pll[3] / 3; 211 break; 212 default: 213 printf("Error: Unknown FMan2 clock select!\n"); 214 case 0: 215 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 216 break; 217 } 218 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 219 #endif /* CONFIG_SYS_DPAA_FMAN */ 220 221 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 222 223 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 224 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 225 & 0xf; 226 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 227 228 sys_info->freq_processor[cpu] = 229 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 230 } 231 #define PME_CLK_SEL 0x80000000 232 #define FM1_CLK_SEL 0x40000000 233 #define FM2_CLK_SEL 0x20000000 234 #define HWA_ASYNC_DIV 0x04000000 235 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 236 #define HWA_CC_PLL 1 237 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 238 #define HWA_CC_PLL 2 239 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 240 #define HWA_CC_PLL 2 241 #else 242 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 243 #endif 244 rcw_tmp = in_be32(&gur->rcwsr[7]); 245 246 #ifdef CONFIG_SYS_DPAA_PME 247 if (rcw_tmp & PME_CLK_SEL) { 248 if (rcw_tmp & HWA_ASYNC_DIV) 249 sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4; 250 else 251 sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2; 252 } else { 253 sys_info->freq_pme = sys_info->freq_systembus / 2; 254 } 255 #endif 256 257 #ifdef CONFIG_SYS_DPAA_FMAN 258 if (rcw_tmp & FM1_CLK_SEL) { 259 if (rcw_tmp & HWA_ASYNC_DIV) 260 sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4; 261 else 262 sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2; 263 } else { 264 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 265 } 266 #if (CONFIG_SYS_NUM_FMAN) == 2 267 if (rcw_tmp & FM2_CLK_SEL) { 268 if (rcw_tmp & HWA_ASYNC_DIV) 269 sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4; 270 else 271 sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2; 272 } else { 273 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 274 } 275 #endif 276 #endif 277 278 #ifdef CONFIG_SYS_DPAA_QBMAN 279 sys_info->freq_qman = sys_info->freq_systembus / 2; 280 #endif 281 282 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 283 284 #else /* CONFIG_FSL_CORENET */ 285 uint plat_ratio, e500_ratio, half_freq_systembus; 286 int i; 287 #ifdef CONFIG_QE 288 __maybe_unused u32 qe_ratio; 289 #endif 290 291 plat_ratio = (gur->porpllsr) & 0x0000003e; 292 plat_ratio >>= 1; 293 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 294 295 /* Divide before multiply to avoid integer 296 * overflow for processor speeds above 2GHz */ 297 half_freq_systembus = sys_info->freq_systembus/2; 298 for (i = 0; i < cpu_numcores(); i++) { 299 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 300 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 301 } 302 303 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 304 sys_info->freq_ddrbus = sys_info->freq_systembus; 305 306 #ifdef CONFIG_DDR_CLK_FREQ 307 { 308 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 309 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 310 if (ddr_ratio != 0x7) 311 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 312 } 313 #endif 314 315 #ifdef CONFIG_QE 316 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 317 sys_info->freq_qe = sys_info->freq_systembus; 318 #else 319 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 320 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 321 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 322 #endif 323 #endif 324 325 #ifdef CONFIG_SYS_DPAA_FMAN 326 sys_info->freq_fman[0] = sys_info->freq_systembus; 327 #endif 328 329 #endif /* CONFIG_FSL_CORENET */ 330 331 #if defined(CONFIG_FSL_LBC) 332 uint lcrr_div; 333 #if defined(CONFIG_SYS_LBC_LCRR) 334 /* We will program LCRR to this value later */ 335 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 336 #else 337 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 338 #endif 339 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 340 #if defined(CONFIG_FSL_CORENET) 341 /* If this is corenet based SoC, bit-representation 342 * for four times the clock divider values. 343 */ 344 lcrr_div *= 4; 345 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 346 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 347 /* 348 * Yes, the entire PQ38 family use the same 349 * bit-representation for twice the clock divider values. 350 */ 351 lcrr_div *= 2; 352 #endif 353 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 354 } else { 355 /* In case anyone cares what the unknown value is */ 356 sys_info->freq_localbus = lcrr_div; 357 } 358 #endif 359 360 #if defined(CONFIG_FSL_IFC) 361 ccr = in_be32(&ifc_regs->ifc_ccr); 362 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 363 364 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 365 #endif 366 } 367 368 369 int get_clocks (void) 370 { 371 sys_info_t sys_info; 372 #ifdef CONFIG_MPC8544 373 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 374 #endif 375 #if defined(CONFIG_CPM2) 376 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 377 uint sccr, dfbrg; 378 379 /* set VCO = 4 * BRG */ 380 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 381 sccr = cpm->im_cpm_intctl.sccr; 382 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 383 #endif 384 get_sys_info (&sys_info); 385 gd->cpu_clk = sys_info.freq_processor[0]; 386 gd->bus_clk = sys_info.freq_systembus; 387 gd->mem_clk = sys_info.freq_ddrbus; 388 gd->arch.lbc_clk = sys_info.freq_localbus; 389 390 #ifdef CONFIG_QE 391 gd->arch.qe_clk = sys_info.freq_qe; 392 gd->arch.brg_clk = gd->arch.qe_clk / 2; 393 #endif 394 /* 395 * The base clock for I2C depends on the actual SOC. Unfortunately, 396 * there is no pattern that can be used to determine the frequency, so 397 * the only choice is to look up the actual SOC number and use the value 398 * for that SOC. This information is taken from application note 399 * AN2919. 400 */ 401 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 402 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 403 defined(CONFIG_P1022) 404 gd->arch.i2c1_clk = sys_info.freq_systembus; 405 #elif defined(CONFIG_MPC8544) 406 /* 407 * On the 8544, the I2C clock is the same as the SEC clock. This can be 408 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 409 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 410 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 411 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 412 */ 413 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 414 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 415 else 416 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 417 #else 418 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 419 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 420 #endif 421 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 422 423 #if defined(CONFIG_FSL_ESDHC) 424 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 425 defined(CONFIG_P1014) 426 gd->arch.sdhc_clk = gd->bus_clk; 427 #else 428 gd->arch.sdhc_clk = gd->bus_clk / 2; 429 #endif 430 #endif /* defined(CONFIG_FSL_ESDHC) */ 431 432 #if defined(CONFIG_CPM2) 433 gd->arch.vco_out = 2*sys_info.freq_systembus; 434 gd->arch.cpm_clk = gd->arch.vco_out / 2; 435 gd->arch.scc_clk = gd->arch.vco_out / 4; 436 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 437 #endif 438 439 if(gd->cpu_clk != 0) return (0); 440 else return (1); 441 } 442 443 444 /******************************************** 445 * get_bus_freq 446 * return system bus freq in Hz 447 *********************************************/ 448 ulong get_bus_freq (ulong dummy) 449 { 450 return gd->bus_clk; 451 } 452 453 /******************************************** 454 * get_ddr_freq 455 * return ddr bus freq in Hz 456 *********************************************/ 457 ulong get_ddr_freq (ulong dummy) 458 { 459 return gd->mem_clk; 460 } 461