1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_CORENET 31 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 32 unsigned int cpu; 33 #ifdef CONFIG_HETROGENOUS_CLUSTERS 34 unsigned int dsp_cpu; 35 uint rcw_tmp1, rcw_tmp2; 36 #endif 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 __maybe_unused u32 svr; 41 42 const u8 core_cplx_PLL[16] = { 43 [ 0] = 0, /* CC1 PPL / 1 */ 44 [ 1] = 0, /* CC1 PPL / 2 */ 45 [ 2] = 0, /* CC1 PPL / 4 */ 46 [ 4] = 1, /* CC2 PPL / 1 */ 47 [ 5] = 1, /* CC2 PPL / 2 */ 48 [ 6] = 1, /* CC2 PPL / 4 */ 49 [ 8] = 2, /* CC3 PPL / 1 */ 50 [ 9] = 2, /* CC3 PPL / 2 */ 51 [10] = 2, /* CC3 PPL / 4 */ 52 [12] = 3, /* CC4 PPL / 1 */ 53 [13] = 3, /* CC4 PPL / 2 */ 54 [14] = 3, /* CC4 PPL / 4 */ 55 }; 56 57 const u8 core_cplx_pll_div[16] = { 58 [ 0] = 1, /* CC1 PPL / 1 */ 59 [ 1] = 2, /* CC1 PPL / 2 */ 60 [ 2] = 4, /* CC1 PPL / 4 */ 61 [ 4] = 1, /* CC2 PPL / 1 */ 62 [ 5] = 2, /* CC2 PPL / 2 */ 63 [ 6] = 4, /* CC2 PPL / 4 */ 64 [ 8] = 1, /* CC3 PPL / 1 */ 65 [ 9] = 2, /* CC3 PPL / 2 */ 66 [10] = 4, /* CC3 PPL / 4 */ 67 [12] = 1, /* CC4 PPL / 1 */ 68 [13] = 2, /* CC4 PPL / 2 */ 69 [14] = 4, /* CC4 PPL / 4 */ 70 }; 71 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 72 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ 73 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) 74 uint rcw_tmp; 75 #endif 76 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 77 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 78 uint mem_pll_rat; 79 80 sys_info->freq_systembus = sysclk; 81 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 82 uint ddr_refclk_sel; 83 unsigned int porsr1_sys_clk; 84 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT 85 & FSL_DCFG_PORSR1_SYSCLK_MASK; 86 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) 87 sys_info->diff_sysclk = 1; 88 else 89 sys_info->diff_sysclk = 0; 90 91 /* 92 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 93 * are driven by separate DDR Refclock or single source 94 * differential clock. 95 */ 96 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> 97 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 98 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 99 /* 100 * For single source clocking, both ddrclock and sysclock 101 * are driven by differential sysclock. 102 */ 103 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) 104 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 105 else 106 #endif 107 #ifdef CONFIG_DDR_CLK_FREQ 108 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 109 #else 110 sys_info->freq_ddrbus = sysclk; 111 #endif 112 113 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 114 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 115 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 116 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 117 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 118 if (mem_pll_rat == 0) { 119 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 120 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 121 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 122 } 123 #endif 124 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 125 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 126 * it uses 6. 127 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 128 */ 129 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ 130 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 131 svr = get_svr(); 132 switch (SVR_SOC_VER(svr)) { 133 case SVR_T4240: 134 case SVR_T4160: 135 case SVR_T4120: 136 case SVR_T4080: 137 if (SVR_MAJ(svr) >= 2) 138 mem_pll_rat *= 2; 139 break; 140 case SVR_T2080: 141 case SVR_T2081: 142 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) 143 mem_pll_rat *= 2; 144 break; 145 default: 146 break; 147 } 148 #endif 149 if (mem_pll_rat > 2) 150 sys_info->freq_ddrbus *= mem_pll_rat; 151 else 152 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 153 154 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 155 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 156 if (ratio[i] > 4) 157 freq_c_pll[i] = sysclk * ratio[i]; 158 else 159 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 160 } 161 162 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 163 /* 164 * As per CHASSIS2 architeture total 12 clusters are posible and 165 * Each cluster has up to 4 cores, sharing the same PLL selection. 166 * The cluster clock assignment is SoC defined. 167 * 168 * Total 4 clock groups are possible with 3 PLLs each. 169 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 170 * clock group B has 3, 4, 6 and so on. 171 * 172 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 173 * depends upon the SoC architeture. Same applies to other 174 * clock groups and clusters. 175 * 176 */ 177 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 178 int cluster = fsl_qoriq_core_to_cluster(cpu); 179 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 180 & 0xf; 181 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 182 cplx_pll += cc_group[cluster] - 1; 183 sys_info->freq_processor[cpu] = 184 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 185 } 186 187 #ifdef CONFIG_HETROGENOUS_CLUSTERS 188 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) { 189 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu); 190 u32 c_pll_sel = (in_be32 191 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27) 192 & 0xf; 193 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 194 cplx_pll += cc_group[dsp_cluster] - 1; 195 sys_info->freq_processor_dsp[dsp_cpu] = 196 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 197 } 198 #endif 199 200 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ 201 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 202 #define FM1_CLK_SEL 0xe0000000 203 #define FM1_CLK_SHIFT 29 204 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 205 #define FM1_CLK_SEL 0x00000007 206 #define FM1_CLK_SHIFT 0 207 #else 208 #define PME_CLK_SEL 0xe0000000 209 #define PME_CLK_SHIFT 29 210 #define FM1_CLK_SEL 0x1c000000 211 #define FM1_CLK_SHIFT 26 212 #endif 213 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 214 #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 215 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; 216 #else 217 rcw_tmp = in_be32(&gur->rcwsr[7]); 218 #endif 219 #endif 220 221 #ifdef CONFIG_SYS_DPAA_PME 222 #ifndef CONFIG_PME_PLAT_CLK_DIV 223 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 224 case 1: 225 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 226 break; 227 case 2: 228 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 229 break; 230 case 3: 231 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 232 break; 233 case 4: 234 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 235 break; 236 case 6: 237 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 238 break; 239 case 7: 240 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 241 break; 242 default: 243 printf("Error: Unknown PME clock select!\n"); 244 case 0: 245 sys_info->freq_pme = sys_info->freq_systembus / 2; 246 break; 247 248 } 249 #else 250 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 251 252 #endif 253 #endif 254 255 #ifdef CONFIG_SYS_DPAA_QBMAN 256 #ifndef CONFIG_QBMAN_CLK_DIV 257 #define CONFIG_QBMAN_CLK_DIV 2 258 #endif 259 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; 260 #endif 261 262 #if defined(CONFIG_SYS_MAPLE) 263 #define CPRI_CLK_SEL 0x1C000000 264 #define CPRI_CLK_SHIFT 26 265 #define CPRI_ALT_CLK_SEL 0x00007000 266 #define CPRI_ALT_CLK_SHIFT 12 267 268 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ 269 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ 270 /* For MAPLE and CPRI frequency */ 271 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) { 272 case 1: 273 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK]; 274 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK]; 275 break; 276 case 2: 277 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; 278 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; 279 break; 280 case 3: 281 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; 282 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; 283 break; 284 case 4: 285 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; 286 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; 287 break; 288 case 5: 289 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) 290 >> CPRI_ALT_CLK_SHIFT) == 6) { 291 sys_info->freq_maple = 292 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; 293 sys_info->freq_cpri = 294 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; 295 } 296 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) 297 >> CPRI_ALT_CLK_SHIFT) == 7) { 298 sys_info->freq_maple = 299 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; 300 sys_info->freq_cpri = 301 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; 302 } 303 break; 304 case 6: 305 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; 306 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; 307 break; 308 case 7: 309 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; 310 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; 311 break; 312 default: 313 printf("Error: Unknown MAPLE/CPRI clock select!\n"); 314 } 315 316 /* For MAPLE ULB and eTVPE frequencies */ 317 #define ULB_CLK_SEL 0x00000038 318 #define ULB_CLK_SHIFT 3 319 #define ETVPE_CLK_SEL 0x00000007 320 #define ETVPE_CLK_SHIFT 0 321 322 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) { 323 case 1: 324 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK]; 325 break; 326 case 2: 327 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2; 328 break; 329 case 3: 330 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3; 331 break; 332 case 4: 333 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4; 334 break; 335 case 5: 336 sys_info->freq_maple_ulb = sys_info->freq_systembus; 337 break; 338 case 6: 339 sys_info->freq_maple_ulb = 340 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2; 341 break; 342 case 7: 343 sys_info->freq_maple_ulb = 344 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3; 345 break; 346 default: 347 printf("Error: Unknown MAPLE ULB clock select!\n"); 348 } 349 350 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) { 351 case 1: 352 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK]; 353 break; 354 case 2: 355 sys_info->freq_maple_etvpe = 356 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2; 357 break; 358 case 3: 359 sys_info->freq_maple_etvpe = 360 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3; 361 break; 362 case 4: 363 sys_info->freq_maple_etvpe = 364 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4; 365 break; 366 case 5: 367 sys_info->freq_maple_etvpe = sys_info->freq_systembus; 368 break; 369 case 6: 370 sys_info->freq_maple_etvpe = 371 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2; 372 break; 373 case 7: 374 sys_info->freq_maple_etvpe = 375 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3; 376 break; 377 default: 378 printf("Error: Unknown MAPLE eTVPE clock select!\n"); 379 } 380 381 #endif 382 383 #ifdef CONFIG_SYS_DPAA_FMAN 384 #ifndef CONFIG_FM_PLAT_CLK_DIV 385 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 386 case 1: 387 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 388 break; 389 case 2: 390 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 391 break; 392 case 3: 393 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 394 break; 395 case 4: 396 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 397 break; 398 case 5: 399 sys_info->freq_fman[0] = sys_info->freq_systembus; 400 break; 401 case 6: 402 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 403 break; 404 case 7: 405 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 406 break; 407 default: 408 printf("Error: Unknown FMan1 clock select!\n"); 409 case 0: 410 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 411 break; 412 } 413 #if (CONFIG_SYS_NUM_FMAN) == 2 414 #ifdef CONFIG_SYS_FM2_CLK 415 #define FM2_CLK_SEL 0x00000038 416 #define FM2_CLK_SHIFT 3 417 rcw_tmp = in_be32(&gur->rcwsr[15]); 418 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 419 case 1: 420 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 421 break; 422 case 2: 423 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 424 break; 425 case 3: 426 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 427 break; 428 case 4: 429 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 430 break; 431 case 5: 432 sys_info->freq_fman[1] = sys_info->freq_systembus; 433 break; 434 case 6: 435 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 436 break; 437 case 7: 438 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 439 break; 440 default: 441 printf("Error: Unknown FMan2 clock select!\n"); 442 case 0: 443 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 444 break; 445 } 446 #endif 447 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 448 #else 449 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 450 #endif 451 #endif 452 453 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 454 #if defined(CONFIG_ARCH_T2080) 455 #define ESDHC_CLK_SEL 0x00000007 456 #define ESDHC_CLK_SHIFT 0 457 #define ESDHC_CLK_RCWSR 15 458 #else /* Support T1040 T1024 by now */ 459 #define ESDHC_CLK_SEL 0xe0000000 460 #define ESDHC_CLK_SHIFT 29 461 #define ESDHC_CLK_RCWSR 7 462 #endif 463 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); 464 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { 465 case 1: 466 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; 467 break; 468 case 2: 469 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; 470 break; 471 case 3: 472 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; 473 break; 474 #if defined(CONFIG_SYS_SDHC_CLK_2_PLL) 475 case 4: 476 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; 477 break; 478 #if defined(CONFIG_ARCH_T2080) 479 case 5: 480 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; 481 break; 482 #endif 483 case 6: 484 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; 485 break; 486 case 7: 487 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; 488 break; 489 #endif 490 default: 491 sys_info->freq_sdhc = 0; 492 printf("Error: Unknown SDHC peripheral clock select!\n"); 493 } 494 #endif 495 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 496 497 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 498 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 499 & 0xf; 500 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 501 502 sys_info->freq_processor[cpu] = 503 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 504 } 505 #define PME_CLK_SEL 0x80000000 506 #define FM1_CLK_SEL 0x40000000 507 #define FM2_CLK_SEL 0x20000000 508 #define HWA_ASYNC_DIV 0x04000000 509 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 510 #define HWA_CC_PLL 1 511 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 512 #define HWA_CC_PLL 2 513 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 514 #define HWA_CC_PLL 2 515 #else 516 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 517 #endif 518 rcw_tmp = in_be32(&gur->rcwsr[7]); 519 520 #ifdef CONFIG_SYS_DPAA_PME 521 if (rcw_tmp & PME_CLK_SEL) { 522 if (rcw_tmp & HWA_ASYNC_DIV) 523 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 524 else 525 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 526 } else { 527 sys_info->freq_pme = sys_info->freq_systembus / 2; 528 } 529 #endif 530 531 #ifdef CONFIG_SYS_DPAA_FMAN 532 if (rcw_tmp & FM1_CLK_SEL) { 533 if (rcw_tmp & HWA_ASYNC_DIV) 534 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 535 else 536 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 537 } else { 538 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 539 } 540 #if (CONFIG_SYS_NUM_FMAN) == 2 541 if (rcw_tmp & FM2_CLK_SEL) { 542 if (rcw_tmp & HWA_ASYNC_DIV) 543 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 544 else 545 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 546 } else { 547 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 548 } 549 #endif 550 #endif 551 552 #ifdef CONFIG_SYS_DPAA_QBMAN 553 sys_info->freq_qman = sys_info->freq_systembus / 2; 554 #endif 555 556 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 557 558 #ifdef CONFIG_U_QE 559 sys_info->freq_qe = sys_info->freq_systembus / 2; 560 #endif 561 562 #else /* CONFIG_FSL_CORENET */ 563 uint plat_ratio, e500_ratio, half_freq_systembus; 564 int i; 565 #ifdef CONFIG_QE 566 __maybe_unused u32 qe_ratio; 567 #endif 568 569 plat_ratio = (gur->porpllsr) & 0x0000003e; 570 plat_ratio >>= 1; 571 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 572 573 /* Divide before multiply to avoid integer 574 * overflow for processor speeds above 2GHz */ 575 half_freq_systembus = sys_info->freq_systembus/2; 576 for (i = 0; i < cpu_numcores(); i++) { 577 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 578 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 579 } 580 581 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 582 sys_info->freq_ddrbus = sys_info->freq_systembus; 583 584 #ifdef CONFIG_DDR_CLK_FREQ 585 { 586 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 587 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 588 if (ddr_ratio != 0x7) 589 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 590 } 591 #endif 592 593 #ifdef CONFIG_QE 594 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) 595 sys_info->freq_qe = sys_info->freq_systembus; 596 #else 597 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 598 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 599 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 600 #endif 601 #endif 602 603 #ifdef CONFIG_SYS_DPAA_FMAN 604 sys_info->freq_fman[0] = sys_info->freq_systembus; 605 #endif 606 607 #endif /* CONFIG_FSL_CORENET */ 608 609 #if defined(CONFIG_FSL_LBC) 610 sys_info->freq_localbus = sys_info->freq_systembus / 611 CONFIG_SYS_FSL_LBC_CLK_DIV; 612 #endif 613 614 #if defined(CONFIG_FSL_IFC) 615 sys_info->freq_localbus = sys_info->freq_systembus / 616 CONFIG_SYS_FSL_IFC_CLK_DIV; 617 #endif 618 } 619 620 621 int get_clocks (void) 622 { 623 sys_info_t sys_info; 624 #ifdef CONFIG_ARCH_MPC8544 625 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 626 #endif 627 #if defined(CONFIG_CPM2) 628 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 629 uint sccr, dfbrg; 630 631 /* set VCO = 4 * BRG */ 632 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 633 sccr = cpm->im_cpm_intctl.sccr; 634 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 635 #endif 636 get_sys_info (&sys_info); 637 gd->cpu_clk = sys_info.freq_processor[0]; 638 gd->bus_clk = sys_info.freq_systembus; 639 gd->mem_clk = sys_info.freq_ddrbus; 640 gd->arch.lbc_clk = sys_info.freq_localbus; 641 642 #ifdef CONFIG_QE 643 gd->arch.qe_clk = sys_info.freq_qe; 644 gd->arch.brg_clk = gd->arch.qe_clk / 2; 645 #endif 646 /* 647 * The base clock for I2C depends on the actual SOC. Unfortunately, 648 * there is no pattern that can be used to determine the frequency, so 649 * the only choice is to look up the actual SOC number and use the value 650 * for that SOC. This information is taken from application note 651 * AN2919. 652 */ 653 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ 654 defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ 655 defined(CONFIG_ARCH_P1022) 656 gd->arch.i2c1_clk = sys_info.freq_systembus; 657 #elif defined(CONFIG_ARCH_MPC8544) 658 /* 659 * On the 8544, the I2C clock is the same as the SEC clock. This can be 660 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 661 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 662 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 663 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 664 */ 665 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 666 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 667 else 668 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 669 #else 670 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 671 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 672 #endif 673 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 674 675 #if defined(CONFIG_FSL_ESDHC) 676 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 677 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; 678 #else 679 #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) 680 gd->arch.sdhc_clk = gd->bus_clk; 681 #else 682 gd->arch.sdhc_clk = gd->bus_clk / 2; 683 #endif 684 #endif 685 #endif /* defined(CONFIG_FSL_ESDHC) */ 686 687 #if defined(CONFIG_CPM2) 688 gd->arch.vco_out = 2*sys_info.freq_systembus; 689 gd->arch.cpm_clk = gd->arch.vco_out / 2; 690 gd->arch.scc_clk = gd->arch.vco_out / 4; 691 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 692 #endif 693 694 if(gd->cpu_clk != 0) return (0); 695 else return (1); 696 } 697 698 699 /******************************************** 700 * get_bus_freq 701 * return system bus freq in Hz 702 *********************************************/ 703 ulong get_bus_freq (ulong dummy) 704 { 705 return gd->bus_clk; 706 } 707 708 /******************************************** 709 * get_ddr_freq 710 * return ddr bus freq in Hz 711 *********************************************/ 712 ulong get_ddr_freq (ulong dummy) 713 { 714 return gd->mem_clk; 715 } 716