xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/speed.c (revision ac1058fd)
1 /*
2  * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * (C) Copyright 2003 Motorola Inc.
5  * Xianghua Xiao, (X.Xiao@motorola.com)
6  *
7  * (C) Copyright 2000
8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #include <common.h>
14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h>
16 #include <asm/processor.h>
17 #include <asm/io.h>
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS	6
24 #endif
25 /* --------------------------------------------------------------- */
26 
27 void get_sys_info(sys_info_t *sys_info)
28 {
29 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 #ifdef CONFIG_FSL_IFC
31 	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
32 	u32 ccr;
33 #endif
34 #ifdef CONFIG_FSL_CORENET
35 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
36 	unsigned int cpu;
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
39 #endif
40 
41 	const u8 core_cplx_PLL[16] = {
42 		[ 0] = 0,	/* CC1 PPL / 1 */
43 		[ 1] = 0,	/* CC1 PPL / 2 */
44 		[ 2] = 0,	/* CC1 PPL / 4 */
45 		[ 4] = 1,	/* CC2 PPL / 1 */
46 		[ 5] = 1,	/* CC2 PPL / 2 */
47 		[ 6] = 1,	/* CC2 PPL / 4 */
48 		[ 8] = 2,	/* CC3 PPL / 1 */
49 		[ 9] = 2,	/* CC3 PPL / 2 */
50 		[10] = 2,	/* CC3 PPL / 4 */
51 		[12] = 3,	/* CC4 PPL / 1 */
52 		[13] = 3,	/* CC4 PPL / 2 */
53 		[14] = 3,	/* CC4 PPL / 4 */
54 	};
55 
56 	const u8 core_cplx_pll_div[16] = {
57 		[ 0] = 1,	/* CC1 PPL / 1 */
58 		[ 1] = 2,	/* CC1 PPL / 2 */
59 		[ 2] = 4,	/* CC1 PPL / 4 */
60 		[ 4] = 1,	/* CC2 PPL / 1 */
61 		[ 5] = 2,	/* CC2 PPL / 2 */
62 		[ 6] = 4,	/* CC2 PPL / 4 */
63 		[ 8] = 1,	/* CC3 PPL / 1 */
64 		[ 9] = 2,	/* CC3 PPL / 2 */
65 		[10] = 4,	/* CC3 PPL / 4 */
66 		[12] = 1,	/* CC4 PPL / 1 */
67 		[13] = 2,	/* CC4 PPL / 2 */
68 		[14] = 4,	/* CC4 PPL / 4 */
69 	};
70 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
72 	uint rcw_tmp;
73 #endif
74 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76 	uint mem_pll_rat;
77 
78 	sys_info->freq_systembus = sysclk;
79 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
80 	uint ddr_refclk_sel;
81 	unsigned int porsr1_sys_clk;
82 	porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
83 						& FSL_DCFG_PORSR1_SYSCLK_MASK;
84 	if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
85 		sys_info->diff_sysclk = 1;
86 	else
87 		sys_info->diff_sysclk = 0;
88 
89 	/*
90 	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
91 	 * are driven by separate DDR Refclock or single source
92 	 * differential clock.
93 	 */
94 	ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
95 		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
96 		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
97 	/*
98 	 * For single source clocking, both ddrclock and sysclock
99 	 * are driven by differential sysclock.
100 	 */
101 	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
102 		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
103 	else
104 #endif
105 #ifdef CONFIG_DDR_CLK_FREQ
106 		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
107 #else
108 		sys_info->freq_ddrbus = sysclk;
109 #endif
110 
111 	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
112 	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
113 			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
114 			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
115 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
116 	if (mem_pll_rat == 0) {
117 		mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
118 			FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
119 			FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
120 	}
121 #endif
122 	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
123 	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
124 	 * it uses 6.
125 	 */
126 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
127 	if (SVR_MAJ(get_svr()) >= 2)
128 		mem_pll_rat *= 2;
129 #endif
130 	if (mem_pll_rat > 2)
131 		sys_info->freq_ddrbus *= mem_pll_rat;
132 	else
133 		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
134 
135 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
136 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
137 		if (ratio[i] > 4)
138 			freq_c_pll[i] = sysclk * ratio[i];
139 		else
140 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
141 	}
142 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
143 	/*
144 	 * As per CHASSIS2 architeture total 12 clusters are posible and
145 	 * Each cluster has up to 4 cores, sharing the same PLL selection.
146 	 * The cluster clock assignment is SoC defined.
147 	 *
148 	 * Total 4 clock groups are possible with 3 PLLs each.
149 	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
150 	 * clock group B has 3, 4, 6 and so on.
151 	 *
152 	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
153 	 * depends upon the SoC architeture. Same applies to other
154 	 * clock groups and clusters.
155 	 *
156 	 */
157 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
158 		int cluster = fsl_qoriq_core_to_cluster(cpu);
159 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
160 				& 0xf;
161 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
162 		cplx_pll += cc_group[cluster] - 1;
163 		sys_info->freq_processor[cpu] =
164 			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
165 	}
166 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
167 	defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
168 #define FM1_CLK_SEL	0xe0000000
169 #define FM1_CLK_SHIFT	29
170 #else
171 #define PME_CLK_SEL	0xe0000000
172 #define PME_CLK_SHIFT	29
173 #define FM1_CLK_SEL	0x1c000000
174 #define FM1_CLK_SHIFT	26
175 #endif
176 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
177 	rcw_tmp = in_be32(&gur->rcwsr[7]);
178 #endif
179 
180 #ifdef CONFIG_SYS_DPAA_PME
181 #ifndef CONFIG_PME_PLAT_CLK_DIV
182 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
183 	case 1:
184 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
185 		break;
186 	case 2:
187 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
188 		break;
189 	case 3:
190 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
191 		break;
192 	case 4:
193 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
194 		break;
195 	case 6:
196 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
197 		break;
198 	case 7:
199 		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
200 		break;
201 	default:
202 		printf("Error: Unknown PME clock select!\n");
203 	case 0:
204 		sys_info->freq_pme = sys_info->freq_systembus / 2;
205 		break;
206 
207 	}
208 #else
209 	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
210 
211 #endif
212 #endif
213 
214 #ifdef CONFIG_SYS_DPAA_QBMAN
215 	sys_info->freq_qman = sys_info->freq_systembus / 2;
216 #endif
217 
218 #ifdef CONFIG_SYS_DPAA_FMAN
219 #ifndef CONFIG_FM_PLAT_CLK_DIV
220 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
221 	case 1:
222 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
223 		break;
224 	case 2:
225 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
226 		break;
227 	case 3:
228 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
229 		break;
230 	case 4:
231 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
232 		break;
233 	case 5:
234 		sys_info->freq_fman[0] = sys_info->freq_systembus;
235 		break;
236 	case 6:
237 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
238 		break;
239 	case 7:
240 		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
241 		break;
242 	default:
243 		printf("Error: Unknown FMan1 clock select!\n");
244 	case 0:
245 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
246 		break;
247 	}
248 #if (CONFIG_SYS_NUM_FMAN) == 2
249 #ifdef CONFIG_SYS_FM2_CLK
250 #define FM2_CLK_SEL	0x00000038
251 #define FM2_CLK_SHIFT	3
252 	rcw_tmp = in_be32(&gur->rcwsr[15]);
253 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
254 	case 1:
255 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
256 		break;
257 	case 2:
258 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
259 		break;
260 	case 3:
261 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
262 		break;
263 	case 4:
264 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
265 		break;
266 	case 5:
267 		sys_info->freq_fman[1] = sys_info->freq_systembus;
268 		break;
269 	case 6:
270 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
271 		break;
272 	case 7:
273 		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
274 		break;
275 	default:
276 		printf("Error: Unknown FMan2 clock select!\n");
277 	case 0:
278 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
279 		break;
280 	}
281 #endif
282 #endif	/* CONFIG_SYS_NUM_FMAN == 2 */
283 #else
284 	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
285 #endif
286 #endif
287 
288 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
289 
290 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
291 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
292 				& 0xf;
293 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
294 
295 		sys_info->freq_processor[cpu] =
296 			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
297 	}
298 #define PME_CLK_SEL	0x80000000
299 #define FM1_CLK_SEL	0x40000000
300 #define FM2_CLK_SEL	0x20000000
301 #define HWA_ASYNC_DIV	0x04000000
302 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
303 #define HWA_CC_PLL	1
304 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
305 #define HWA_CC_PLL	2
306 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
307 #define HWA_CC_PLL	2
308 #else
309 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
310 #endif
311 	rcw_tmp = in_be32(&gur->rcwsr[7]);
312 
313 #ifdef CONFIG_SYS_DPAA_PME
314 	if (rcw_tmp & PME_CLK_SEL) {
315 		if (rcw_tmp & HWA_ASYNC_DIV)
316 			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
317 		else
318 			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
319 	} else {
320 		sys_info->freq_pme = sys_info->freq_systembus / 2;
321 	}
322 #endif
323 
324 #ifdef CONFIG_SYS_DPAA_FMAN
325 	if (rcw_tmp & FM1_CLK_SEL) {
326 		if (rcw_tmp & HWA_ASYNC_DIV)
327 			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
328 		else
329 			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
330 	} else {
331 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
332 	}
333 #if (CONFIG_SYS_NUM_FMAN) == 2
334 	if (rcw_tmp & FM2_CLK_SEL) {
335 		if (rcw_tmp & HWA_ASYNC_DIV)
336 			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
337 		else
338 			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
339 	} else {
340 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
341 	}
342 #endif
343 #endif
344 
345 #ifdef CONFIG_SYS_DPAA_QBMAN
346 	sys_info->freq_qman = sys_info->freq_systembus / 2;
347 #endif
348 
349 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
350 
351 #ifdef CONFIG_U_QE
352 	sys_info->freq_qe =  sys_info->freq_systembus / 2;
353 #endif
354 
355 #else /* CONFIG_FSL_CORENET */
356 	uint plat_ratio, e500_ratio, half_freq_systembus;
357 	int i;
358 #ifdef CONFIG_QE
359 	__maybe_unused u32 qe_ratio;
360 #endif
361 
362 	plat_ratio = (gur->porpllsr) & 0x0000003e;
363 	plat_ratio >>= 1;
364 	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
365 
366 	/* Divide before multiply to avoid integer
367 	 * overflow for processor speeds above 2GHz */
368 	half_freq_systembus = sys_info->freq_systembus/2;
369 	for (i = 0; i < cpu_numcores(); i++) {
370 		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
371 		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
372 	}
373 
374 	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
375 	sys_info->freq_ddrbus = sys_info->freq_systembus;
376 
377 #ifdef CONFIG_DDR_CLK_FREQ
378 	{
379 		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
380 			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
381 		if (ddr_ratio != 0x7)
382 			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
383 	}
384 #endif
385 
386 #ifdef CONFIG_QE
387 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
388 	sys_info->freq_qe =  sys_info->freq_systembus;
389 #else
390 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
391 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
392 	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
393 #endif
394 #endif
395 
396 #ifdef CONFIG_SYS_DPAA_FMAN
397 		sys_info->freq_fman[0] = sys_info->freq_systembus;
398 #endif
399 
400 #endif /* CONFIG_FSL_CORENET */
401 
402 #if defined(CONFIG_FSL_LBC)
403 	uint lcrr_div;
404 #if defined(CONFIG_SYS_LBC_LCRR)
405 	/* We will program LCRR to this value later */
406 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
407 #else
408 	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
409 #endif
410 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
411 #if defined(CONFIG_FSL_CORENET)
412 		/* If this is corenet based SoC, bit-representation
413 		 * for four times the clock divider values.
414 		 */
415 		lcrr_div *= 4;
416 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
417     !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
418 		/*
419 		 * Yes, the entire PQ38 family use the same
420 		 * bit-representation for twice the clock divider values.
421 		 */
422 		lcrr_div *= 2;
423 #endif
424 		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
425 	} else {
426 		/* In case anyone cares what the unknown value is */
427 		sys_info->freq_localbus = lcrr_div;
428 	}
429 #endif
430 
431 #if defined(CONFIG_FSL_IFC)
432 	ccr = in_be32(&ifc_regs->ifc_ccr);
433 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
434 
435 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
436 #endif
437 }
438 
439 
440 int get_clocks (void)
441 {
442 	sys_info_t sys_info;
443 #ifdef CONFIG_MPC8544
444 	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
445 #endif
446 #if defined(CONFIG_CPM2)
447 	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
448 	uint sccr, dfbrg;
449 
450 	/* set VCO = 4 * BRG */
451 	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
452 	sccr = cpm->im_cpm_intctl.sccr;
453 	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
454 #endif
455 	get_sys_info (&sys_info);
456 	gd->cpu_clk = sys_info.freq_processor[0];
457 	gd->bus_clk = sys_info.freq_systembus;
458 	gd->mem_clk = sys_info.freq_ddrbus;
459 	gd->arch.lbc_clk = sys_info.freq_localbus;
460 
461 #ifdef CONFIG_QE
462 	gd->arch.qe_clk = sys_info.freq_qe;
463 	gd->arch.brg_clk = gd->arch.qe_clk / 2;
464 #endif
465 	/*
466 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
467 	 * there is no pattern that can be used to determine the frequency, so
468 	 * the only choice is to look up the actual SOC number and use the value
469 	 * for that SOC. This information is taken from application note
470 	 * AN2919.
471 	 */
472 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
473 	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
474 	defined(CONFIG_P1022)
475 	gd->arch.i2c1_clk = sys_info.freq_systembus;
476 #elif defined(CONFIG_MPC8544)
477 	/*
478 	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
479 	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
480 	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
481 	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
482 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
483 	 */
484 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
485 		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
486 	else
487 		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
488 #else
489 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
490 	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
491 #endif
492 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
493 
494 #if defined(CONFIG_FSL_ESDHC)
495 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
496        defined(CONFIG_P1014)
497 	gd->arch.sdhc_clk = gd->bus_clk;
498 #else
499 	gd->arch.sdhc_clk = gd->bus_clk / 2;
500 #endif
501 #endif /* defined(CONFIG_FSL_ESDHC) */
502 
503 #if defined(CONFIG_CPM2)
504 	gd->arch.vco_out = 2*sys_info.freq_systembus;
505 	gd->arch.cpm_clk = gd->arch.vco_out / 2;
506 	gd->arch.scc_clk = gd->arch.vco_out / 4;
507 	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
508 #endif
509 
510 	if(gd->cpu_clk != 0) return (0);
511 	else return (1);
512 }
513 
514 
515 /********************************************
516  * get_bus_freq
517  * return system bus freq in Hz
518  *********************************************/
519 ulong get_bus_freq (ulong dummy)
520 {
521 	return gd->bus_clk;
522 }
523 
524 /********************************************
525  * get_ddr_freq
526  * return ddr bus freq in Hz
527  *********************************************/
528 ulong get_ddr_freq (ulong dummy)
529 {
530 	return gd->mem_clk;
531 }
532