1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 78 uint single_src; 79 #endif 80 81 sys_info->freq_systembus = sysclk; 82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 83 /* 84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 85 * are driven by separate DDR Refclock or single source 86 * differential clock. 87 */ 88 single_src = (in_be32(&gur->rcwsr[5]) >> 89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 91 /* 92 * For single source clocking, both ddrclock and syclock 93 * are driven by differential sysclock. 94 */ 95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { 96 printf("Single Source Clock Configuration\n"); 97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 98 } else 99 #endif 100 #ifdef CONFIG_DDR_CLK_FREQ 101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 102 #else 103 sys_info->freq_ddrbus = sysclk; 104 #endif 105 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 112 * it uses 6. 113 */ 114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 115 if (SVR_MAJ(get_svr()) >= 2) 116 mem_pll_rat *= 2; 117 #endif 118 if (mem_pll_rat > 2) 119 sys_info->freq_ddrbus *= mem_pll_rat; 120 else 121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 122 123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 125 if (ratio[i] > 4) 126 freq_c_pll[i] = sysclk * ratio[i]; 127 else 128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 129 } 130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 131 /* 132 * As per CHASSIS2 architeture total 12 clusters are posible and 133 * Each cluster has up to 4 cores, sharing the same PLL selection. 134 * The cluster clock assignment is SoC defined. 135 * 136 * Total 4 clock groups are possible with 3 PLLs each. 137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 138 * clock group B has 3, 4, 6 and so on. 139 * 140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 141 * depends upon the SoC architeture. Same applies to other 142 * clock groups and clusters. 143 * 144 */ 145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 146 int cluster = fsl_qoriq_core_to_cluster(cpu); 147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 148 & 0xf; 149 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 150 cplx_pll += cc_group[cluster] - 1; 151 sys_info->freq_processor[cpu] = 152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 153 } 154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) 155 #define FM1_CLK_SEL 0xe0000000 156 #define FM1_CLK_SHIFT 29 157 #else 158 #define PME_CLK_SEL 0xe0000000 159 #define PME_CLK_SHIFT 29 160 #define FM1_CLK_SEL 0x1c000000 161 #define FM1_CLK_SHIFT 26 162 #endif 163 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 164 rcw_tmp = in_be32(&gur->rcwsr[7]); 165 #endif 166 167 #ifdef CONFIG_SYS_DPAA_PME 168 #ifndef CONFIG_PME_PLAT_CLK_DIV 169 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 170 case 1: 171 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 172 break; 173 case 2: 174 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 175 break; 176 case 3: 177 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 178 break; 179 case 4: 180 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 181 break; 182 case 6: 183 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 184 break; 185 case 7: 186 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 187 break; 188 default: 189 printf("Error: Unknown PME clock select!\n"); 190 case 0: 191 sys_info->freq_pme = sys_info->freq_systembus / 2; 192 break; 193 194 } 195 #else 196 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 197 198 #endif 199 #endif 200 201 #ifdef CONFIG_SYS_DPAA_QBMAN 202 sys_info->freq_qman = sys_info->freq_systembus / 2; 203 #endif 204 205 #ifdef CONFIG_SYS_DPAA_FMAN 206 #ifndef CONFIG_FM_PLAT_CLK_DIV 207 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 208 case 1: 209 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 210 break; 211 case 2: 212 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 213 break; 214 case 3: 215 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 216 break; 217 case 4: 218 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 219 break; 220 case 5: 221 sys_info->freq_fman[0] = sys_info->freq_systembus; 222 break; 223 case 6: 224 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 225 break; 226 case 7: 227 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 228 break; 229 default: 230 printf("Error: Unknown FMan1 clock select!\n"); 231 case 0: 232 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 233 break; 234 } 235 #if (CONFIG_SYS_NUM_FMAN) == 2 236 #ifdef CONFIG_SYS_FM2_CLK 237 #define FM2_CLK_SEL 0x00000038 238 #define FM2_CLK_SHIFT 3 239 rcw_tmp = in_be32(&gur->rcwsr[15]); 240 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 241 case 1: 242 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 243 break; 244 case 2: 245 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 246 break; 247 case 3: 248 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 249 break; 250 case 4: 251 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 252 break; 253 case 5: 254 sys_info->freq_fman[1] = sys_info->freq_systembus; 255 break; 256 case 6: 257 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 258 break; 259 case 7: 260 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 261 break; 262 default: 263 printf("Error: Unknown FMan2 clock select!\n"); 264 case 0: 265 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 266 break; 267 } 268 #endif 269 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 270 #else 271 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 272 #endif 273 #endif 274 275 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 276 277 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 278 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 279 & 0xf; 280 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 281 282 sys_info->freq_processor[cpu] = 283 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 284 } 285 #define PME_CLK_SEL 0x80000000 286 #define FM1_CLK_SEL 0x40000000 287 #define FM2_CLK_SEL 0x20000000 288 #define HWA_ASYNC_DIV 0x04000000 289 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 290 #define HWA_CC_PLL 1 291 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 292 #define HWA_CC_PLL 2 293 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 294 #define HWA_CC_PLL 2 295 #else 296 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 297 #endif 298 rcw_tmp = in_be32(&gur->rcwsr[7]); 299 300 #ifdef CONFIG_SYS_DPAA_PME 301 if (rcw_tmp & PME_CLK_SEL) { 302 if (rcw_tmp & HWA_ASYNC_DIV) 303 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 304 else 305 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 306 } else { 307 sys_info->freq_pme = sys_info->freq_systembus / 2; 308 } 309 #endif 310 311 #ifdef CONFIG_SYS_DPAA_FMAN 312 if (rcw_tmp & FM1_CLK_SEL) { 313 if (rcw_tmp & HWA_ASYNC_DIV) 314 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 315 else 316 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 317 } else { 318 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 319 } 320 #if (CONFIG_SYS_NUM_FMAN) == 2 321 if (rcw_tmp & FM2_CLK_SEL) { 322 if (rcw_tmp & HWA_ASYNC_DIV) 323 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 324 else 325 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 326 } else { 327 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 328 } 329 #endif 330 #endif 331 332 #ifdef CONFIG_SYS_DPAA_QBMAN 333 sys_info->freq_qman = sys_info->freq_systembus / 2; 334 #endif 335 336 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 337 338 #else /* CONFIG_FSL_CORENET */ 339 uint plat_ratio, e500_ratio, half_freq_systembus; 340 int i; 341 #ifdef CONFIG_QE 342 __maybe_unused u32 qe_ratio; 343 #endif 344 345 plat_ratio = (gur->porpllsr) & 0x0000003e; 346 plat_ratio >>= 1; 347 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 348 349 /* Divide before multiply to avoid integer 350 * overflow for processor speeds above 2GHz */ 351 half_freq_systembus = sys_info->freq_systembus/2; 352 for (i = 0; i < cpu_numcores(); i++) { 353 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 354 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 355 } 356 357 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 358 sys_info->freq_ddrbus = sys_info->freq_systembus; 359 360 #ifdef CONFIG_DDR_CLK_FREQ 361 { 362 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 363 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 364 if (ddr_ratio != 0x7) 365 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 366 } 367 #endif 368 369 #ifdef CONFIG_QE 370 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 371 sys_info->freq_qe = sys_info->freq_systembus; 372 #else 373 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 374 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 375 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 376 #endif 377 #endif 378 379 #ifdef CONFIG_SYS_DPAA_FMAN 380 sys_info->freq_fman[0] = sys_info->freq_systembus; 381 #endif 382 383 #endif /* CONFIG_FSL_CORENET */ 384 385 #if defined(CONFIG_FSL_LBC) 386 uint lcrr_div; 387 #if defined(CONFIG_SYS_LBC_LCRR) 388 /* We will program LCRR to this value later */ 389 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 390 #else 391 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 392 #endif 393 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 394 #if defined(CONFIG_FSL_CORENET) 395 /* If this is corenet based SoC, bit-representation 396 * for four times the clock divider values. 397 */ 398 lcrr_div *= 4; 399 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 400 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 401 /* 402 * Yes, the entire PQ38 family use the same 403 * bit-representation for twice the clock divider values. 404 */ 405 lcrr_div *= 2; 406 #endif 407 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 408 } else { 409 /* In case anyone cares what the unknown value is */ 410 sys_info->freq_localbus = lcrr_div; 411 } 412 #endif 413 414 #if defined(CONFIG_FSL_IFC) 415 ccr = in_be32(&ifc_regs->ifc_ccr); 416 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 417 418 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 419 #endif 420 } 421 422 423 int get_clocks (void) 424 { 425 sys_info_t sys_info; 426 #ifdef CONFIG_MPC8544 427 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 428 #endif 429 #if defined(CONFIG_CPM2) 430 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 431 uint sccr, dfbrg; 432 433 /* set VCO = 4 * BRG */ 434 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 435 sccr = cpm->im_cpm_intctl.sccr; 436 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 437 #endif 438 get_sys_info (&sys_info); 439 gd->cpu_clk = sys_info.freq_processor[0]; 440 gd->bus_clk = sys_info.freq_systembus; 441 gd->mem_clk = sys_info.freq_ddrbus; 442 gd->arch.lbc_clk = sys_info.freq_localbus; 443 444 #ifdef CONFIG_QE 445 gd->arch.qe_clk = sys_info.freq_qe; 446 gd->arch.brg_clk = gd->arch.qe_clk / 2; 447 #endif 448 /* 449 * The base clock for I2C depends on the actual SOC. Unfortunately, 450 * there is no pattern that can be used to determine the frequency, so 451 * the only choice is to look up the actual SOC number and use the value 452 * for that SOC. This information is taken from application note 453 * AN2919. 454 */ 455 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 456 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 457 defined(CONFIG_P1022) 458 gd->arch.i2c1_clk = sys_info.freq_systembus; 459 #elif defined(CONFIG_MPC8544) 460 /* 461 * On the 8544, the I2C clock is the same as the SEC clock. This can be 462 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 463 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 464 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 465 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 466 */ 467 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 468 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 469 else 470 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 471 #else 472 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 473 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 474 #endif 475 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 476 477 #if defined(CONFIG_FSL_ESDHC) 478 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 479 defined(CONFIG_P1014) 480 gd->arch.sdhc_clk = gd->bus_clk; 481 #else 482 gd->arch.sdhc_clk = gd->bus_clk / 2; 483 #endif 484 #endif /* defined(CONFIG_FSL_ESDHC) */ 485 486 #if defined(CONFIG_CPM2) 487 gd->arch.vco_out = 2*sys_info.freq_systembus; 488 gd->arch.cpm_clk = gd->arch.vco_out / 2; 489 gd->arch.scc_clk = gd->arch.vco_out / 4; 490 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 491 #endif 492 493 if(gd->cpu_clk != 0) return (0); 494 else return (1); 495 } 496 497 498 /******************************************** 499 * get_bus_freq 500 * return system bus freq in Hz 501 *********************************************/ 502 ulong get_bus_freq (ulong dummy) 503 { 504 return gd->bus_clk; 505 } 506 507 /******************************************** 508 * get_ddr_freq 509 * return ddr bus freq in Hz 510 *********************************************/ 511 ulong get_ddr_freq (ulong dummy) 512 { 513 return gd->mem_clk; 514 } 515