1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_HETROGENOUS_CLUSTERS 38 unsigned int dsp_cpu; 39 uint rcw_tmp1, rcw_tmp2; 40 #endif 41 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 43 #endif 44 __maybe_unused u32 svr; 45 46 const u8 core_cplx_PLL[16] = { 47 [ 0] = 0, /* CC1 PPL / 1 */ 48 [ 1] = 0, /* CC1 PPL / 2 */ 49 [ 2] = 0, /* CC1 PPL / 4 */ 50 [ 4] = 1, /* CC2 PPL / 1 */ 51 [ 5] = 1, /* CC2 PPL / 2 */ 52 [ 6] = 1, /* CC2 PPL / 4 */ 53 [ 8] = 2, /* CC3 PPL / 1 */ 54 [ 9] = 2, /* CC3 PPL / 2 */ 55 [10] = 2, /* CC3 PPL / 4 */ 56 [12] = 3, /* CC4 PPL / 1 */ 57 [13] = 3, /* CC4 PPL / 2 */ 58 [14] = 3, /* CC4 PPL / 4 */ 59 }; 60 61 const u8 core_cplx_pll_div[16] = { 62 [ 0] = 1, /* CC1 PPL / 1 */ 63 [ 1] = 2, /* CC1 PPL / 2 */ 64 [ 2] = 4, /* CC1 PPL / 4 */ 65 [ 4] = 1, /* CC2 PPL / 1 */ 66 [ 5] = 2, /* CC2 PPL / 2 */ 67 [ 6] = 4, /* CC2 PPL / 4 */ 68 [ 8] = 1, /* CC3 PPL / 1 */ 69 [ 9] = 2, /* CC3 PPL / 2 */ 70 [10] = 4, /* CC3 PPL / 4 */ 71 [12] = 1, /* CC4 PPL / 1 */ 72 [13] = 2, /* CC4 PPL / 2 */ 73 [14] = 4, /* CC4 PPL / 4 */ 74 }; 75 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 76 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ 77 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) 78 uint rcw_tmp; 79 #endif 80 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 81 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 82 uint mem_pll_rat; 83 84 sys_info->freq_systembus = sysclk; 85 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 86 uint ddr_refclk_sel; 87 unsigned int porsr1_sys_clk; 88 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT 89 & FSL_DCFG_PORSR1_SYSCLK_MASK; 90 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) 91 sys_info->diff_sysclk = 1; 92 else 93 sys_info->diff_sysclk = 0; 94 95 /* 96 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 97 * are driven by separate DDR Refclock or single source 98 * differential clock. 99 */ 100 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> 101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 102 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 103 /* 104 * For single source clocking, both ddrclock and sysclock 105 * are driven by differential sysclock. 106 */ 107 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) 108 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 109 else 110 #endif 111 #ifdef CONFIG_DDR_CLK_FREQ 112 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 113 #else 114 sys_info->freq_ddrbus = sysclk; 115 #endif 116 117 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 120 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 121 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 122 if (mem_pll_rat == 0) { 123 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 125 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 126 } 127 #endif 128 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 129 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 130 * it uses 6. 131 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 132 */ 133 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 134 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ 135 defined(CONFIG_PPC_T2081) 136 svr = get_svr(); 137 switch (SVR_SOC_VER(svr)) { 138 case SVR_T4240: 139 case SVR_T4160: 140 case SVR_T4120: 141 case SVR_T4080: 142 if (SVR_MAJ(svr) >= 2) 143 mem_pll_rat *= 2; 144 break; 145 case SVR_T2080: 146 case SVR_T2081: 147 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) 148 mem_pll_rat *= 2; 149 break; 150 default: 151 break; 152 } 153 #endif 154 if (mem_pll_rat > 2) 155 sys_info->freq_ddrbus *= mem_pll_rat; 156 else 157 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 158 159 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 160 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 161 if (ratio[i] > 4) 162 freq_c_pll[i] = sysclk * ratio[i]; 163 else 164 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 165 } 166 167 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 168 /* 169 * As per CHASSIS2 architeture total 12 clusters are posible and 170 * Each cluster has up to 4 cores, sharing the same PLL selection. 171 * The cluster clock assignment is SoC defined. 172 * 173 * Total 4 clock groups are possible with 3 PLLs each. 174 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 175 * clock group B has 3, 4, 6 and so on. 176 * 177 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 178 * depends upon the SoC architeture. Same applies to other 179 * clock groups and clusters. 180 * 181 */ 182 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 183 int cluster = fsl_qoriq_core_to_cluster(cpu); 184 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 185 & 0xf; 186 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 187 cplx_pll += cc_group[cluster] - 1; 188 sys_info->freq_processor[cpu] = 189 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 190 } 191 192 #ifdef CONFIG_HETROGENOUS_CLUSTERS 193 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) { 194 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu); 195 u32 c_pll_sel = (in_be32 196 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27) 197 & 0xf; 198 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 199 cplx_pll += cc_group[dsp_cluster] - 1; 200 sys_info->freq_processor_dsp[dsp_cpu] = 201 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 202 } 203 #endif 204 205 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ 206 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 207 #define FM1_CLK_SEL 0xe0000000 208 #define FM1_CLK_SHIFT 29 209 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_ARCH_T1023) 210 #define FM1_CLK_SEL 0x00000007 211 #define FM1_CLK_SHIFT 0 212 #else 213 #define PME_CLK_SEL 0xe0000000 214 #define PME_CLK_SHIFT 29 215 #define FM1_CLK_SEL 0x1c000000 216 #define FM1_CLK_SHIFT 26 217 #endif 218 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 219 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_ARCH_T1023) 220 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; 221 #else 222 rcw_tmp = in_be32(&gur->rcwsr[7]); 223 #endif 224 #endif 225 226 #ifdef CONFIG_SYS_DPAA_PME 227 #ifndef CONFIG_PME_PLAT_CLK_DIV 228 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 229 case 1: 230 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 231 break; 232 case 2: 233 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 234 break; 235 case 3: 236 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 237 break; 238 case 4: 239 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 240 break; 241 case 6: 242 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 243 break; 244 case 7: 245 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 246 break; 247 default: 248 printf("Error: Unknown PME clock select!\n"); 249 case 0: 250 sys_info->freq_pme = sys_info->freq_systembus / 2; 251 break; 252 253 } 254 #else 255 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 256 257 #endif 258 #endif 259 260 #ifdef CONFIG_SYS_DPAA_QBMAN 261 #ifndef CONFIG_QBMAN_CLK_DIV 262 #define CONFIG_QBMAN_CLK_DIV 2 263 #endif 264 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; 265 #endif 266 267 #if defined(CONFIG_SYS_MAPLE) 268 #define CPRI_CLK_SEL 0x1C000000 269 #define CPRI_CLK_SHIFT 26 270 #define CPRI_ALT_CLK_SEL 0x00007000 271 #define CPRI_ALT_CLK_SHIFT 12 272 273 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ 274 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ 275 /* For MAPLE and CPRI frequency */ 276 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) { 277 case 1: 278 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK]; 279 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK]; 280 break; 281 case 2: 282 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; 283 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; 284 break; 285 case 3: 286 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; 287 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; 288 break; 289 case 4: 290 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; 291 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; 292 break; 293 case 5: 294 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) 295 >> CPRI_ALT_CLK_SHIFT) == 6) { 296 sys_info->freq_maple = 297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; 298 sys_info->freq_cpri = 299 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; 300 } 301 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) 302 >> CPRI_ALT_CLK_SHIFT) == 7) { 303 sys_info->freq_maple = 304 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; 305 sys_info->freq_cpri = 306 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; 307 } 308 break; 309 case 6: 310 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; 311 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; 312 break; 313 case 7: 314 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; 315 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; 316 break; 317 default: 318 printf("Error: Unknown MAPLE/CPRI clock select!\n"); 319 } 320 321 /* For MAPLE ULB and eTVPE frequencies */ 322 #define ULB_CLK_SEL 0x00000038 323 #define ULB_CLK_SHIFT 3 324 #define ETVPE_CLK_SEL 0x00000007 325 #define ETVPE_CLK_SHIFT 0 326 327 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) { 328 case 1: 329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK]; 330 break; 331 case 2: 332 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2; 333 break; 334 case 3: 335 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3; 336 break; 337 case 4: 338 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4; 339 break; 340 case 5: 341 sys_info->freq_maple_ulb = sys_info->freq_systembus; 342 break; 343 case 6: 344 sys_info->freq_maple_ulb = 345 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2; 346 break; 347 case 7: 348 sys_info->freq_maple_ulb = 349 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3; 350 break; 351 default: 352 printf("Error: Unknown MAPLE ULB clock select!\n"); 353 } 354 355 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) { 356 case 1: 357 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK]; 358 break; 359 case 2: 360 sys_info->freq_maple_etvpe = 361 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2; 362 break; 363 case 3: 364 sys_info->freq_maple_etvpe = 365 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3; 366 break; 367 case 4: 368 sys_info->freq_maple_etvpe = 369 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4; 370 break; 371 case 5: 372 sys_info->freq_maple_etvpe = sys_info->freq_systembus; 373 break; 374 case 6: 375 sys_info->freq_maple_etvpe = 376 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2; 377 break; 378 case 7: 379 sys_info->freq_maple_etvpe = 380 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3; 381 break; 382 default: 383 printf("Error: Unknown MAPLE eTVPE clock select!\n"); 384 } 385 386 #endif 387 388 #ifdef CONFIG_SYS_DPAA_FMAN 389 #ifndef CONFIG_FM_PLAT_CLK_DIV 390 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 391 case 1: 392 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 393 break; 394 case 2: 395 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 396 break; 397 case 3: 398 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 399 break; 400 case 4: 401 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 402 break; 403 case 5: 404 sys_info->freq_fman[0] = sys_info->freq_systembus; 405 break; 406 case 6: 407 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 408 break; 409 case 7: 410 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 411 break; 412 default: 413 printf("Error: Unknown FMan1 clock select!\n"); 414 case 0: 415 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 416 break; 417 } 418 #if (CONFIG_SYS_NUM_FMAN) == 2 419 #ifdef CONFIG_SYS_FM2_CLK 420 #define FM2_CLK_SEL 0x00000038 421 #define FM2_CLK_SHIFT 3 422 rcw_tmp = in_be32(&gur->rcwsr[15]); 423 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 424 case 1: 425 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 426 break; 427 case 2: 428 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 429 break; 430 case 3: 431 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 432 break; 433 case 4: 434 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 435 break; 436 case 5: 437 sys_info->freq_fman[1] = sys_info->freq_systembus; 438 break; 439 case 6: 440 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 441 break; 442 case 7: 443 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 444 break; 445 default: 446 printf("Error: Unknown FMan2 clock select!\n"); 447 case 0: 448 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 449 break; 450 } 451 #endif 452 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 453 #else 454 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 455 #endif 456 #endif 457 458 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 459 #if defined(CONFIG_PPC_T2080) 460 #define ESDHC_CLK_SEL 0x00000007 461 #define ESDHC_CLK_SHIFT 0 462 #define ESDHC_CLK_RCWSR 15 463 #else /* Support T1040 T1024 by now */ 464 #define ESDHC_CLK_SEL 0xe0000000 465 #define ESDHC_CLK_SHIFT 29 466 #define ESDHC_CLK_RCWSR 7 467 #endif 468 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); 469 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { 470 case 1: 471 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; 472 break; 473 case 2: 474 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; 475 break; 476 case 3: 477 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; 478 break; 479 #if defined(CONFIG_SYS_SDHC_CLK_2_PLL) 480 case 4: 481 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; 482 break; 483 #if defined(CONFIG_PPC_T2080) 484 case 5: 485 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; 486 break; 487 #endif 488 case 6: 489 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; 490 break; 491 case 7: 492 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; 493 break; 494 #endif 495 default: 496 sys_info->freq_sdhc = 0; 497 printf("Error: Unknown SDHC peripheral clock select!\n"); 498 } 499 #endif 500 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 501 502 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 503 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 504 & 0xf; 505 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 506 507 sys_info->freq_processor[cpu] = 508 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 509 } 510 #define PME_CLK_SEL 0x80000000 511 #define FM1_CLK_SEL 0x40000000 512 #define FM2_CLK_SEL 0x20000000 513 #define HWA_ASYNC_DIV 0x04000000 514 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 515 #define HWA_CC_PLL 1 516 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 517 #define HWA_CC_PLL 2 518 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 519 #define HWA_CC_PLL 2 520 #else 521 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 522 #endif 523 rcw_tmp = in_be32(&gur->rcwsr[7]); 524 525 #ifdef CONFIG_SYS_DPAA_PME 526 if (rcw_tmp & PME_CLK_SEL) { 527 if (rcw_tmp & HWA_ASYNC_DIV) 528 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 529 else 530 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 531 } else { 532 sys_info->freq_pme = sys_info->freq_systembus / 2; 533 } 534 #endif 535 536 #ifdef CONFIG_SYS_DPAA_FMAN 537 if (rcw_tmp & FM1_CLK_SEL) { 538 if (rcw_tmp & HWA_ASYNC_DIV) 539 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 540 else 541 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 542 } else { 543 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 544 } 545 #if (CONFIG_SYS_NUM_FMAN) == 2 546 if (rcw_tmp & FM2_CLK_SEL) { 547 if (rcw_tmp & HWA_ASYNC_DIV) 548 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 549 else 550 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 551 } else { 552 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 553 } 554 #endif 555 #endif 556 557 #ifdef CONFIG_SYS_DPAA_QBMAN 558 sys_info->freq_qman = sys_info->freq_systembus / 2; 559 #endif 560 561 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 562 563 #ifdef CONFIG_U_QE 564 sys_info->freq_qe = sys_info->freq_systembus / 2; 565 #endif 566 567 #else /* CONFIG_FSL_CORENET */ 568 uint plat_ratio, e500_ratio, half_freq_systembus; 569 int i; 570 #ifdef CONFIG_QE 571 __maybe_unused u32 qe_ratio; 572 #endif 573 574 plat_ratio = (gur->porpllsr) & 0x0000003e; 575 plat_ratio >>= 1; 576 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 577 578 /* Divide before multiply to avoid integer 579 * overflow for processor speeds above 2GHz */ 580 half_freq_systembus = sys_info->freq_systembus/2; 581 for (i = 0; i < cpu_numcores(); i++) { 582 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 583 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 584 } 585 586 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 587 sys_info->freq_ddrbus = sys_info->freq_systembus; 588 589 #ifdef CONFIG_DDR_CLK_FREQ 590 { 591 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 592 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 593 if (ddr_ratio != 0x7) 594 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 595 } 596 #endif 597 598 #ifdef CONFIG_QE 599 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) 600 sys_info->freq_qe = sys_info->freq_systembus; 601 #else 602 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 603 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 604 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 605 #endif 606 #endif 607 608 #ifdef CONFIG_SYS_DPAA_FMAN 609 sys_info->freq_fman[0] = sys_info->freq_systembus; 610 #endif 611 612 #endif /* CONFIG_FSL_CORENET */ 613 614 #if defined(CONFIG_FSL_LBC) 615 uint lcrr_div; 616 #if defined(CONFIG_SYS_LBC_LCRR) 617 /* We will program LCRR to this value later */ 618 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 619 #else 620 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 621 #endif 622 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 623 #if defined(CONFIG_FSL_CORENET) 624 /* If this is corenet based SoC, bit-representation 625 * for four times the clock divider values. 626 */ 627 lcrr_div *= 4; 628 #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ 629 !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) 630 /* 631 * Yes, the entire PQ38 family use the same 632 * bit-representation for twice the clock divider values. 633 */ 634 lcrr_div *= 2; 635 #endif 636 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 637 } else { 638 /* In case anyone cares what the unknown value is */ 639 sys_info->freq_localbus = lcrr_div; 640 } 641 #endif 642 643 #if defined(CONFIG_FSL_IFC) 644 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); 645 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 646 647 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 648 #endif 649 } 650 651 652 int get_clocks (void) 653 { 654 sys_info_t sys_info; 655 #ifdef CONFIG_ARCH_MPC8544 656 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 657 #endif 658 #if defined(CONFIG_CPM2) 659 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 660 uint sccr, dfbrg; 661 662 /* set VCO = 4 * BRG */ 663 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 664 sccr = cpm->im_cpm_intctl.sccr; 665 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 666 #endif 667 get_sys_info (&sys_info); 668 gd->cpu_clk = sys_info.freq_processor[0]; 669 gd->bus_clk = sys_info.freq_systembus; 670 gd->mem_clk = sys_info.freq_ddrbus; 671 gd->arch.lbc_clk = sys_info.freq_localbus; 672 673 #ifdef CONFIG_QE 674 gd->arch.qe_clk = sys_info.freq_qe; 675 gd->arch.brg_clk = gd->arch.qe_clk / 2; 676 #endif 677 /* 678 * The base clock for I2C depends on the actual SOC. Unfortunately, 679 * there is no pattern that can be used to determine the frequency, so 680 * the only choice is to look up the actual SOC number and use the value 681 * for that SOC. This information is taken from application note 682 * AN2919. 683 */ 684 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ 685 defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ 686 defined(CONFIG_ARCH_P1022) 687 gd->arch.i2c1_clk = sys_info.freq_systembus; 688 #elif defined(CONFIG_ARCH_MPC8544) 689 /* 690 * On the 8544, the I2C clock is the same as the SEC clock. This can be 691 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 692 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 693 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 694 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 695 */ 696 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 697 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 698 else 699 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 700 #else 701 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 702 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 703 #endif 704 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 705 706 #if defined(CONFIG_FSL_ESDHC) 707 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 708 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; 709 #else 710 #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) 711 gd->arch.sdhc_clk = gd->bus_clk; 712 #else 713 gd->arch.sdhc_clk = gd->bus_clk / 2; 714 #endif 715 #endif 716 #endif /* defined(CONFIG_FSL_ESDHC) */ 717 718 #if defined(CONFIG_CPM2) 719 gd->arch.vco_out = 2*sys_info.freq_systembus; 720 gd->arch.cpm_clk = gd->arch.vco_out / 2; 721 gd->arch.scc_clk = gd->arch.vco_out / 4; 722 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 723 #endif 724 725 if(gd->cpu_clk != 0) return (0); 726 else return (1); 727 } 728 729 730 /******************************************** 731 * get_bus_freq 732 * return system bus freq in Hz 733 *********************************************/ 734 ulong get_bus_freq (ulong dummy) 735 { 736 return gd->bus_clk; 737 } 738 739 /******************************************** 740 * get_ddr_freq 741 * return ddr bus freq in Hz 742 *********************************************/ 743 ulong get_ddr_freq (ulong dummy) 744 { 745 return gd->mem_clk; 746 } 747