1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 78 sys_info->freq_systembus = sysclk; 79 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 80 uint ddr_refclk_sel; 81 unsigned int porsr1_sys_clk; 82 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT 83 & FSL_DCFG_PORSR1_SYSCLK_MASK; 84 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) 85 sys_info->diff_sysclk = 1; 86 else 87 sys_info->diff_sysclk = 0; 88 89 /* 90 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 91 * are driven by separate DDR Refclock or single source 92 * differential clock. 93 */ 94 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> 95 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 96 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 97 /* 98 * For single source clocking, both ddrclock and sysclock 99 * are driven by differential sysclock. 100 */ 101 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) 102 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 103 else 104 #endif 105 #ifdef CONFIG_DDR_CLK_FREQ 106 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 107 #else 108 sys_info->freq_ddrbus = sysclk; 109 #endif 110 111 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 112 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 113 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 114 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 115 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 116 if (mem_pll_rat == 0) { 117 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 118 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 120 } 121 #endif 122 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 123 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 124 * it uses 6. 125 */ 126 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 127 defined(CONFIG_PPC_T4080) 128 if (SVR_MAJ(get_svr()) >= 2) 129 mem_pll_rat *= 2; 130 #endif 131 if (mem_pll_rat > 2) 132 sys_info->freq_ddrbus *= mem_pll_rat; 133 else 134 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 135 136 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 137 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 138 if (ratio[i] > 4) 139 freq_c_pll[i] = sysclk * ratio[i]; 140 else 141 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 142 } 143 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 144 /* 145 * As per CHASSIS2 architeture total 12 clusters are posible and 146 * Each cluster has up to 4 cores, sharing the same PLL selection. 147 * The cluster clock assignment is SoC defined. 148 * 149 * Total 4 clock groups are possible with 3 PLLs each. 150 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 151 * clock group B has 3, 4, 6 and so on. 152 * 153 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 154 * depends upon the SoC architeture. Same applies to other 155 * clock groups and clusters. 156 * 157 */ 158 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 159 int cluster = fsl_qoriq_core_to_cluster(cpu); 160 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 161 & 0xf; 162 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 163 cplx_pll += cc_group[cluster] - 1; 164 sys_info->freq_processor[cpu] = 165 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 166 } 167 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ 168 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 169 #define FM1_CLK_SEL 0xe0000000 170 #define FM1_CLK_SHIFT 29 171 #else 172 #define PME_CLK_SEL 0xe0000000 173 #define PME_CLK_SHIFT 29 174 #define FM1_CLK_SEL 0x1c000000 175 #define FM1_CLK_SHIFT 26 176 #endif 177 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 178 rcw_tmp = in_be32(&gur->rcwsr[7]); 179 #endif 180 181 #ifdef CONFIG_SYS_DPAA_PME 182 #ifndef CONFIG_PME_PLAT_CLK_DIV 183 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 184 case 1: 185 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 186 break; 187 case 2: 188 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 189 break; 190 case 3: 191 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 192 break; 193 case 4: 194 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 195 break; 196 case 6: 197 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 198 break; 199 case 7: 200 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 201 break; 202 default: 203 printf("Error: Unknown PME clock select!\n"); 204 case 0: 205 sys_info->freq_pme = sys_info->freq_systembus / 2; 206 break; 207 208 } 209 #else 210 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 211 212 #endif 213 #endif 214 215 #ifdef CONFIG_SYS_DPAA_QBMAN 216 sys_info->freq_qman = sys_info->freq_systembus / 2; 217 #endif 218 219 #ifdef CONFIG_SYS_DPAA_FMAN 220 #ifndef CONFIG_FM_PLAT_CLK_DIV 221 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 222 case 1: 223 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 224 break; 225 case 2: 226 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 227 break; 228 case 3: 229 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 230 break; 231 case 4: 232 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 233 break; 234 case 5: 235 sys_info->freq_fman[0] = sys_info->freq_systembus; 236 break; 237 case 6: 238 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 239 break; 240 case 7: 241 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 242 break; 243 default: 244 printf("Error: Unknown FMan1 clock select!\n"); 245 case 0: 246 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 247 break; 248 } 249 #if (CONFIG_SYS_NUM_FMAN) == 2 250 #ifdef CONFIG_SYS_FM2_CLK 251 #define FM2_CLK_SEL 0x00000038 252 #define FM2_CLK_SHIFT 3 253 rcw_tmp = in_be32(&gur->rcwsr[15]); 254 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 255 case 1: 256 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 257 break; 258 case 2: 259 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 260 break; 261 case 3: 262 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 263 break; 264 case 4: 265 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 266 break; 267 case 5: 268 sys_info->freq_fman[1] = sys_info->freq_systembus; 269 break; 270 case 6: 271 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 272 break; 273 case 7: 274 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 275 break; 276 default: 277 printf("Error: Unknown FMan2 clock select!\n"); 278 case 0: 279 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 280 break; 281 } 282 #endif 283 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 284 #else 285 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 286 #endif 287 #endif 288 289 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 290 291 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 292 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 293 & 0xf; 294 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 295 296 sys_info->freq_processor[cpu] = 297 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 298 } 299 #define PME_CLK_SEL 0x80000000 300 #define FM1_CLK_SEL 0x40000000 301 #define FM2_CLK_SEL 0x20000000 302 #define HWA_ASYNC_DIV 0x04000000 303 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 304 #define HWA_CC_PLL 1 305 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 306 #define HWA_CC_PLL 2 307 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 308 #define HWA_CC_PLL 2 309 #else 310 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 311 #endif 312 rcw_tmp = in_be32(&gur->rcwsr[7]); 313 314 #ifdef CONFIG_SYS_DPAA_PME 315 if (rcw_tmp & PME_CLK_SEL) { 316 if (rcw_tmp & HWA_ASYNC_DIV) 317 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 318 else 319 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 320 } else { 321 sys_info->freq_pme = sys_info->freq_systembus / 2; 322 } 323 #endif 324 325 #ifdef CONFIG_SYS_DPAA_FMAN 326 if (rcw_tmp & FM1_CLK_SEL) { 327 if (rcw_tmp & HWA_ASYNC_DIV) 328 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 329 else 330 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 331 } else { 332 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 333 } 334 #if (CONFIG_SYS_NUM_FMAN) == 2 335 if (rcw_tmp & FM2_CLK_SEL) { 336 if (rcw_tmp & HWA_ASYNC_DIV) 337 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 338 else 339 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 340 } else { 341 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 342 } 343 #endif 344 #endif 345 346 #ifdef CONFIG_SYS_DPAA_QBMAN 347 sys_info->freq_qman = sys_info->freq_systembus / 2; 348 #endif 349 350 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 351 352 #ifdef CONFIG_U_QE 353 sys_info->freq_qe = sys_info->freq_systembus / 2; 354 #endif 355 356 #else /* CONFIG_FSL_CORENET */ 357 uint plat_ratio, e500_ratio, half_freq_systembus; 358 int i; 359 #ifdef CONFIG_QE 360 __maybe_unused u32 qe_ratio; 361 #endif 362 363 plat_ratio = (gur->porpllsr) & 0x0000003e; 364 plat_ratio >>= 1; 365 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 366 367 /* Divide before multiply to avoid integer 368 * overflow for processor speeds above 2GHz */ 369 half_freq_systembus = sys_info->freq_systembus/2; 370 for (i = 0; i < cpu_numcores(); i++) { 371 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 372 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 373 } 374 375 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 376 sys_info->freq_ddrbus = sys_info->freq_systembus; 377 378 #ifdef CONFIG_DDR_CLK_FREQ 379 { 380 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 381 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 382 if (ddr_ratio != 0x7) 383 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 384 } 385 #endif 386 387 #ifdef CONFIG_QE 388 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 389 sys_info->freq_qe = sys_info->freq_systembus; 390 #else 391 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 392 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 393 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 394 #endif 395 #endif 396 397 #ifdef CONFIG_SYS_DPAA_FMAN 398 sys_info->freq_fman[0] = sys_info->freq_systembus; 399 #endif 400 401 #endif /* CONFIG_FSL_CORENET */ 402 403 #if defined(CONFIG_FSL_LBC) 404 uint lcrr_div; 405 #if defined(CONFIG_SYS_LBC_LCRR) 406 /* We will program LCRR to this value later */ 407 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 408 #else 409 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 410 #endif 411 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 412 #if defined(CONFIG_FSL_CORENET) 413 /* If this is corenet based SoC, bit-representation 414 * for four times the clock divider values. 415 */ 416 lcrr_div *= 4; 417 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 418 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 419 /* 420 * Yes, the entire PQ38 family use the same 421 * bit-representation for twice the clock divider values. 422 */ 423 lcrr_div *= 2; 424 #endif 425 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 426 } else { 427 /* In case anyone cares what the unknown value is */ 428 sys_info->freq_localbus = lcrr_div; 429 } 430 #endif 431 432 #if defined(CONFIG_FSL_IFC) 433 ccr = in_be32(&ifc_regs->ifc_ccr); 434 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 435 436 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 437 #endif 438 } 439 440 441 int get_clocks (void) 442 { 443 sys_info_t sys_info; 444 #ifdef CONFIG_MPC8544 445 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 446 #endif 447 #if defined(CONFIG_CPM2) 448 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 449 uint sccr, dfbrg; 450 451 /* set VCO = 4 * BRG */ 452 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 453 sccr = cpm->im_cpm_intctl.sccr; 454 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 455 #endif 456 get_sys_info (&sys_info); 457 gd->cpu_clk = sys_info.freq_processor[0]; 458 gd->bus_clk = sys_info.freq_systembus; 459 gd->mem_clk = sys_info.freq_ddrbus; 460 gd->arch.lbc_clk = sys_info.freq_localbus; 461 462 #ifdef CONFIG_QE 463 gd->arch.qe_clk = sys_info.freq_qe; 464 gd->arch.brg_clk = gd->arch.qe_clk / 2; 465 #endif 466 /* 467 * The base clock for I2C depends on the actual SOC. Unfortunately, 468 * there is no pattern that can be used to determine the frequency, so 469 * the only choice is to look up the actual SOC number and use the value 470 * for that SOC. This information is taken from application note 471 * AN2919. 472 */ 473 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 474 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 475 defined(CONFIG_P1022) 476 gd->arch.i2c1_clk = sys_info.freq_systembus; 477 #elif defined(CONFIG_MPC8544) 478 /* 479 * On the 8544, the I2C clock is the same as the SEC clock. This can be 480 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 481 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 482 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 483 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 484 */ 485 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 486 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 487 else 488 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 489 #else 490 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 491 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 492 #endif 493 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 494 495 #if defined(CONFIG_FSL_ESDHC) 496 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 497 defined(CONFIG_P1014) 498 gd->arch.sdhc_clk = gd->bus_clk; 499 #else 500 gd->arch.sdhc_clk = gd->bus_clk / 2; 501 #endif 502 #endif /* defined(CONFIG_FSL_ESDHC) */ 503 504 #if defined(CONFIG_CPM2) 505 gd->arch.vco_out = 2*sys_info.freq_systembus; 506 gd->arch.cpm_clk = gd->arch.vco_out / 2; 507 gd->arch.scc_clk = gd->arch.vco_out / 4; 508 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 509 #endif 510 511 if(gd->cpu_clk != 0) return (0); 512 else return (1); 513 } 514 515 516 /******************************************** 517 * get_bus_freq 518 * return system bus freq in Hz 519 *********************************************/ 520 ulong get_bus_freq (ulong dummy) 521 { 522 return gd->bus_clk; 523 } 524 525 /******************************************** 526 * get_ddr_freq 527 * return ddr bus freq in Hz 528 *********************************************/ 529 ulong get_ddr_freq (ulong dummy) 530 { 531 return gd->mem_clk; 532 } 533