1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <ppc_asm.tmpl> 31 #include <linux/compiler.h> 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* --------------------------------------------------------------- */ 38 39 void get_sys_info (sys_info_t * sysInfo) 40 { 41 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42 #ifdef CONFIG_FSL_CORENET 43 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 44 unsigned int cpu; 45 46 const u8 core_cplx_PLL[16] = { 47 [ 0] = 0, /* CC1 PPL / 1 */ 48 [ 1] = 0, /* CC1 PPL / 2 */ 49 [ 2] = 0, /* CC1 PPL / 4 */ 50 [ 4] = 1, /* CC2 PPL / 1 */ 51 [ 5] = 1, /* CC2 PPL / 2 */ 52 [ 6] = 1, /* CC2 PPL / 4 */ 53 [ 8] = 2, /* CC3 PPL / 1 */ 54 [ 9] = 2, /* CC3 PPL / 2 */ 55 [10] = 2, /* CC3 PPL / 4 */ 56 [12] = 3, /* CC4 PPL / 1 */ 57 [13] = 3, /* CC4 PPL / 2 */ 58 [14] = 3, /* CC4 PPL / 4 */ 59 }; 60 61 const u8 core_cplx_PLL_div[16] = { 62 [ 0] = 1, /* CC1 PPL / 1 */ 63 [ 1] = 2, /* CC1 PPL / 2 */ 64 [ 2] = 4, /* CC1 PPL / 4 */ 65 [ 4] = 1, /* CC2 PPL / 1 */ 66 [ 5] = 2, /* CC2 PPL / 2 */ 67 [ 6] = 4, /* CC2 PPL / 4 */ 68 [ 8] = 1, /* CC3 PPL / 1 */ 69 [ 9] = 2, /* CC3 PPL / 2 */ 70 [10] = 4, /* CC3 PPL / 4 */ 71 [12] = 1, /* CC4 PPL / 1 */ 72 [13] = 2, /* CC4 PPL / 2 */ 73 [14] = 4, /* CC4 PPL / 4 */ 74 }; 75 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; 76 uint ratio[4]; 77 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 78 uint mem_pll_rat; 79 80 sysInfo->freqSystemBus = sysclk; 81 sysInfo->freqDDRBus = sysclk; 82 83 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 84 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; 85 if (mem_pll_rat > 2) 86 sysInfo->freqDDRBus *= mem_pll_rat; 87 else 88 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; 89 90 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 91 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 92 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 93 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 94 for (i = 0; i < 4; i++) { 95 if (ratio[i] > 4) 96 freqCC_PLL[i] = sysclk * ratio[i]; 97 else 98 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; 99 } 100 rcw_tmp = in_be32(&gur->rcwsr[3]); 101 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 102 u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; 103 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 104 105 sysInfo->freqProcessor[cpu] = 106 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; 107 } 108 109 #define PME_CLK_SEL 0x80000000 110 #define FM1_CLK_SEL 0x40000000 111 #define FM2_CLK_SEL 0x20000000 112 #define HWA_ASYNC_DIV 0x04000000 113 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 114 #define HWA_CC_PLL 1 115 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 116 #define HWA_CC_PLL 2 117 #else 118 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 119 #endif 120 rcw_tmp = in_be32(&gur->rcwsr[7]); 121 122 #ifdef CONFIG_SYS_DPAA_PME 123 if (rcw_tmp & PME_CLK_SEL) { 124 if (rcw_tmp & HWA_ASYNC_DIV) 125 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; 126 else 127 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; 128 } else { 129 sysInfo->freqPME = sysInfo->freqSystemBus / 2; 130 } 131 #endif 132 133 #ifdef CONFIG_SYS_DPAA_FMAN 134 if (rcw_tmp & FM1_CLK_SEL) { 135 if (rcw_tmp & HWA_ASYNC_DIV) 136 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; 137 else 138 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; 139 } else { 140 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; 141 } 142 #if (CONFIG_SYS_NUM_FMAN) == 2 143 if (rcw_tmp & FM2_CLK_SEL) { 144 if (rcw_tmp & HWA_ASYNC_DIV) 145 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; 146 else 147 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; 148 } else { 149 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; 150 } 151 #endif 152 #endif 153 154 #else 155 uint plat_ratio,e500_ratio,half_freqSystemBus; 156 #if defined(CONFIG_FSL_LBC) 157 uint lcrr_div; 158 #endif 159 int i; 160 #ifdef CONFIG_QE 161 __maybe_unused u32 qe_ratio; 162 #endif 163 164 plat_ratio = (gur->porpllsr) & 0x0000003e; 165 plat_ratio >>= 1; 166 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; 167 168 /* Divide before multiply to avoid integer 169 * overflow for processor speeds above 2GHz */ 170 half_freqSystemBus = sysInfo->freqSystemBus/2; 171 for (i = 0; i < cpu_numcores(); i++) { 172 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 173 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; 174 } 175 176 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ 177 sysInfo->freqDDRBus = sysInfo->freqSystemBus; 178 179 #ifdef CONFIG_DDR_CLK_FREQ 180 { 181 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 182 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 183 if (ddr_ratio != 0x7) 184 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 185 } 186 #endif 187 188 #ifdef CONFIG_QE 189 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 190 defined(CONFIG_P1021) || defined(CONFIG_P1025) 191 sysInfo->freqQE = sysInfo->freqSystemBus; 192 #else 193 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 194 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 195 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; 196 #endif 197 #endif 198 199 #ifdef CONFIG_SYS_DPAA_FMAN 200 sysInfo->freqFMan[0] = sysInfo->freqSystemBus; 201 #endif 202 203 #endif /* CONFIG_FSL_CORENET */ 204 205 #if defined(CONFIG_FSL_LBC) 206 #if defined(CONFIG_SYS_LBC_LCRR) 207 /* We will program LCRR to this value later */ 208 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 209 #else 210 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 211 #endif 212 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 213 #if defined(CONFIG_FSL_CORENET) 214 /* If this is corenet based SoC, bit-representation 215 * for four times the clock divider values. 216 */ 217 lcrr_div *= 4; 218 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 219 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 220 /* 221 * Yes, the entire PQ38 family use the same 222 * bit-representation for twice the clock divider values. 223 */ 224 lcrr_div *= 2; 225 #endif 226 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; 227 } else { 228 /* In case anyone cares what the unknown value is */ 229 sysInfo->freqLocalBus = lcrr_div; 230 } 231 #endif 232 } 233 234 235 int get_clocks (void) 236 { 237 sys_info_t sys_info; 238 #ifdef CONFIG_MPC8544 239 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 240 #endif 241 #if defined(CONFIG_CPM2) 242 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 243 uint sccr, dfbrg; 244 245 /* set VCO = 4 * BRG */ 246 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 247 sccr = cpm->im_cpm_intctl.sccr; 248 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 249 #endif 250 get_sys_info (&sys_info); 251 gd->cpu_clk = sys_info.freqProcessor[0]; 252 gd->bus_clk = sys_info.freqSystemBus; 253 gd->mem_clk = sys_info.freqDDRBus; 254 gd->lbc_clk = sys_info.freqLocalBus; 255 256 #ifdef CONFIG_QE 257 gd->qe_clk = sys_info.freqQE; 258 gd->brg_clk = gd->qe_clk / 2; 259 #endif 260 /* 261 * The base clock for I2C depends on the actual SOC. Unfortunately, 262 * there is no pattern that can be used to determine the frequency, so 263 * the only choice is to look up the actual SOC number and use the value 264 * for that SOC. This information is taken from application note 265 * AN2919. 266 */ 267 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 268 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) 269 gd->i2c1_clk = sys_info.freqSystemBus; 270 #elif defined(CONFIG_MPC8544) 271 /* 272 * On the 8544, the I2C clock is the same as the SEC clock. This can be 273 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 274 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 275 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 276 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 277 */ 278 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 279 gd->i2c1_clk = sys_info.freqSystemBus / 3; 280 else 281 gd->i2c1_clk = sys_info.freqSystemBus / 2; 282 #else 283 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 284 gd->i2c1_clk = sys_info.freqSystemBus / 2; 285 #endif 286 gd->i2c2_clk = gd->i2c1_clk; 287 288 #if defined(CONFIG_FSL_ESDHC) 289 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 290 defined(CONFIG_P1014) 291 gd->sdhc_clk = gd->bus_clk; 292 #else 293 gd->sdhc_clk = gd->bus_clk / 2; 294 #endif 295 #endif /* defined(CONFIG_FSL_ESDHC) */ 296 297 #if defined(CONFIG_CPM2) 298 gd->vco_out = 2*sys_info.freqSystemBus; 299 gd->cpm_clk = gd->vco_out / 2; 300 gd->scc_clk = gd->vco_out / 4; 301 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); 302 #endif 303 304 if(gd->cpu_clk != 0) return (0); 305 else return (1); 306 } 307 308 309 /******************************************** 310 * get_bus_freq 311 * return system bus freq in Hz 312 *********************************************/ 313 ulong get_bus_freq (ulong dummy) 314 { 315 return gd->bus_clk; 316 } 317 318 /******************************************** 319 * get_ddr_freq 320 * return ddr bus freq in Hz 321 *********************************************/ 322 ulong get_ddr_freq (ulong dummy) 323 { 324 return gd->mem_clk; 325 } 326