1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <ppc_asm.tmpl> 31 #include <linux/compiler.h> 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* --------------------------------------------------------------- */ 38 39 void get_sys_info (sys_info_t * sysInfo) 40 { 41 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42 #ifdef CONFIG_FSL_CORENET 43 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 44 45 const u8 core_cplx_PLL[16] = { 46 [ 0] = 0, /* CC1 PPL / 1 */ 47 [ 1] = 0, /* CC1 PPL / 2 */ 48 [ 2] = 0, /* CC1 PPL / 4 */ 49 [ 4] = 1, /* CC2 PPL / 1 */ 50 [ 5] = 1, /* CC2 PPL / 2 */ 51 [ 6] = 1, /* CC2 PPL / 4 */ 52 [ 8] = 2, /* CC3 PPL / 1 */ 53 [ 9] = 2, /* CC3 PPL / 2 */ 54 [10] = 2, /* CC3 PPL / 4 */ 55 [12] = 3, /* CC4 PPL / 1 */ 56 [13] = 3, /* CC4 PPL / 2 */ 57 [14] = 3, /* CC4 PPL / 4 */ 58 }; 59 60 const u8 core_cplx_PLL_div[16] = { 61 [ 0] = 1, /* CC1 PPL / 1 */ 62 [ 1] = 2, /* CC1 PPL / 2 */ 63 [ 2] = 4, /* CC1 PPL / 4 */ 64 [ 4] = 1, /* CC2 PPL / 1 */ 65 [ 5] = 2, /* CC2 PPL / 2 */ 66 [ 6] = 4, /* CC2 PPL / 4 */ 67 [ 8] = 1, /* CC3 PPL / 1 */ 68 [ 9] = 2, /* CC3 PPL / 2 */ 69 [10] = 4, /* CC3 PPL / 4 */ 70 [12] = 1, /* CC4 PPL / 1 */ 71 [13] = 2, /* CC4 PPL / 2 */ 72 [14] = 4, /* CC4 PPL / 4 */ 73 }; 74 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; 75 uint ratio[4]; 76 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 77 uint mem_pll_rat; 78 79 sysInfo->freqSystemBus = sysclk; 80 sysInfo->freqDDRBus = sysclk; 81 82 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 83 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; 84 if (mem_pll_rat > 2) 85 sysInfo->freqDDRBus *= mem_pll_rat; 86 else 87 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; 88 89 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 90 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 91 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 92 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 93 for (i = 0; i < 4; i++) { 94 if (ratio[i] > 4) 95 freqCC_PLL[i] = sysclk * ratio[i]; 96 else 97 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; 98 } 99 rcw_tmp = in_be32(&gur->rcwsr[3]); 100 for (i = 0; i < cpu_numcores(); i++) { 101 u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; 102 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 103 104 sysInfo->freqProcessor[i] = 105 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; 106 } 107 108 #define PME_CLK_SEL 0x80000000 109 #define FM1_CLK_SEL 0x40000000 110 #define FM2_CLK_SEL 0x20000000 111 #define HWA_ASYNC_DIV 0x04000000 112 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 113 #define HWA_CC_PLL 1 114 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 115 #define HWA_CC_PLL 2 116 #else 117 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 118 #endif 119 rcw_tmp = in_be32(&gur->rcwsr[7]); 120 121 #ifdef CONFIG_SYS_DPAA_PME 122 if (rcw_tmp & PME_CLK_SEL) { 123 if (rcw_tmp & HWA_ASYNC_DIV) 124 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; 125 else 126 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; 127 } else { 128 sysInfo->freqPME = sysInfo->freqSystemBus / 2; 129 } 130 #endif 131 132 #ifdef CONFIG_SYS_DPAA_FMAN 133 if (rcw_tmp & FM1_CLK_SEL) { 134 if (rcw_tmp & HWA_ASYNC_DIV) 135 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; 136 else 137 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; 138 } else { 139 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; 140 } 141 #if (CONFIG_SYS_NUM_FMAN) == 2 142 if (rcw_tmp & FM2_CLK_SEL) { 143 if (rcw_tmp & HWA_ASYNC_DIV) 144 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; 145 else 146 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; 147 } else { 148 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; 149 } 150 #endif 151 #endif 152 153 #else 154 uint plat_ratio,e500_ratio,half_freqSystemBus; 155 #if defined(CONFIG_FSL_LBC) 156 uint lcrr_div; 157 #endif 158 int i; 159 #ifdef CONFIG_QE 160 __maybe_unused u32 qe_ratio; 161 #endif 162 163 plat_ratio = (gur->porpllsr) & 0x0000003e; 164 plat_ratio >>= 1; 165 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; 166 167 /* Divide before multiply to avoid integer 168 * overflow for processor speeds above 2GHz */ 169 half_freqSystemBus = sysInfo->freqSystemBus/2; 170 for (i = 0; i < cpu_numcores(); i++) { 171 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 172 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; 173 } 174 175 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ 176 sysInfo->freqDDRBus = sysInfo->freqSystemBus; 177 178 #ifdef CONFIG_DDR_CLK_FREQ 179 { 180 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 181 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 182 if (ddr_ratio != 0x7) 183 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 184 } 185 #endif 186 187 #ifdef CONFIG_QE 188 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 189 defined(CONFIG_P1021) || defined(CONFIG_P1025) 190 sysInfo->freqQE = sysInfo->freqSystemBus; 191 #else 192 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 193 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 194 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; 195 #endif 196 #endif 197 198 #ifdef CONFIG_SYS_DPAA_FMAN 199 sysInfo->freqFMan[0] = sysInfo->freqSystemBus; 200 #endif 201 202 #endif /* CONFIG_FSL_CORENET */ 203 204 #if defined(CONFIG_FSL_LBC) 205 #if defined(CONFIG_SYS_LBC_LCRR) 206 /* We will program LCRR to this value later */ 207 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 208 #else 209 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 210 #endif 211 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 212 #if defined(CONFIG_FSL_CORENET) 213 /* If this is corenet based SoC, bit-representation 214 * for four times the clock divider values. 215 */ 216 lcrr_div *= 4; 217 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 218 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 219 /* 220 * Yes, the entire PQ38 family use the same 221 * bit-representation for twice the clock divider values. 222 */ 223 lcrr_div *= 2; 224 #endif 225 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; 226 } else { 227 /* In case anyone cares what the unknown value is */ 228 sysInfo->freqLocalBus = lcrr_div; 229 } 230 #endif 231 } 232 233 234 int get_clocks (void) 235 { 236 sys_info_t sys_info; 237 #ifdef CONFIG_MPC8544 238 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 239 #endif 240 #if defined(CONFIG_CPM2) 241 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 242 uint sccr, dfbrg; 243 244 /* set VCO = 4 * BRG */ 245 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 246 sccr = cpm->im_cpm_intctl.sccr; 247 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 248 #endif 249 get_sys_info (&sys_info); 250 gd->cpu_clk = sys_info.freqProcessor[0]; 251 gd->bus_clk = sys_info.freqSystemBus; 252 gd->mem_clk = sys_info.freqDDRBus; 253 gd->lbc_clk = sys_info.freqLocalBus; 254 255 #ifdef CONFIG_QE 256 gd->qe_clk = sys_info.freqQE; 257 gd->brg_clk = gd->qe_clk / 2; 258 #endif 259 /* 260 * The base clock for I2C depends on the actual SOC. Unfortunately, 261 * there is no pattern that can be used to determine the frequency, so 262 * the only choice is to look up the actual SOC number and use the value 263 * for that SOC. This information is taken from application note 264 * AN2919. 265 */ 266 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 267 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) 268 gd->i2c1_clk = sys_info.freqSystemBus; 269 #elif defined(CONFIG_MPC8544) 270 /* 271 * On the 8544, the I2C clock is the same as the SEC clock. This can be 272 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 273 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 274 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 275 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 276 */ 277 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 278 gd->i2c1_clk = sys_info.freqSystemBus / 3; 279 else 280 gd->i2c1_clk = sys_info.freqSystemBus / 2; 281 #else 282 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 283 gd->i2c1_clk = sys_info.freqSystemBus / 2; 284 #endif 285 gd->i2c2_clk = gd->i2c1_clk; 286 287 #if defined(CONFIG_FSL_ESDHC) 288 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 289 defined(CONFIG_P1014) 290 gd->sdhc_clk = gd->bus_clk; 291 #else 292 gd->sdhc_clk = gd->bus_clk / 2; 293 #endif 294 #endif /* defined(CONFIG_FSL_ESDHC) */ 295 296 #if defined(CONFIG_CPM2) 297 gd->vco_out = 2*sys_info.freqSystemBus; 298 gd->cpm_clk = gd->vco_out / 2; 299 gd->scc_clk = gd->vco_out / 4; 300 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); 301 #endif 302 303 if(gd->cpu_clk != 0) return (0); 304 else return (1); 305 } 306 307 308 /******************************************** 309 * get_bus_freq 310 * return system bus freq in Hz 311 *********************************************/ 312 ulong get_bus_freq (ulong dummy) 313 { 314 return gd->bus_clk; 315 } 316 317 /******************************************** 318 * get_ddr_freq 319 * return ddr bus freq in Hz 320 *********************************************/ 321 ulong get_ddr_freq (ulong dummy) 322 { 323 return gd->mem_clk; 324 } 325