1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 78 uint single_src; 79 #endif 80 81 sys_info->freq_systembus = sysclk; 82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 83 /* 84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 85 * are driven by separate DDR Refclock or single source 86 * differential clock. 87 */ 88 single_src = (in_be32(&gur->rcwsr[5]) >> 89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 91 /* 92 * For single source clocking, both ddrclock and syclock 93 * are driven by differential sysclock. 94 */ 95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { 96 printf("Single Source Clock Configuration\n"); 97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 98 } else 99 #endif 100 #ifdef CONFIG_DDR_CLK_FREQ 101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 102 #else 103 sys_info->freq_ddrbus = sysclk; 104 #endif 105 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 110 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 111 if (mem_pll_rat == 0) { 112 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 113 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 114 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 115 } 116 #endif 117 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 118 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 119 * it uses 6. 120 */ 121 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 122 if (SVR_MAJ(get_svr()) >= 2) 123 mem_pll_rat *= 2; 124 #endif 125 if (mem_pll_rat > 2) 126 sys_info->freq_ddrbus *= mem_pll_rat; 127 else 128 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 129 130 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 131 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 132 if (ratio[i] > 4) 133 freq_c_pll[i] = sysclk * ratio[i]; 134 else 135 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 136 } 137 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 138 /* 139 * As per CHASSIS2 architeture total 12 clusters are posible and 140 * Each cluster has up to 4 cores, sharing the same PLL selection. 141 * The cluster clock assignment is SoC defined. 142 * 143 * Total 4 clock groups are possible with 3 PLLs each. 144 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 145 * clock group B has 3, 4, 6 and so on. 146 * 147 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 148 * depends upon the SoC architeture. Same applies to other 149 * clock groups and clusters. 150 * 151 */ 152 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 153 int cluster = fsl_qoriq_core_to_cluster(cpu); 154 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 155 & 0xf; 156 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 157 cplx_pll += cc_group[cluster] - 1; 158 sys_info->freq_processor[cpu] = 159 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 160 } 161 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \ 162 defined(CONFIG_PPC_T2081) 163 #define FM1_CLK_SEL 0xe0000000 164 #define FM1_CLK_SHIFT 29 165 #else 166 #define PME_CLK_SEL 0xe0000000 167 #define PME_CLK_SHIFT 29 168 #define FM1_CLK_SEL 0x1c000000 169 #define FM1_CLK_SHIFT 26 170 #endif 171 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 172 rcw_tmp = in_be32(&gur->rcwsr[7]); 173 #endif 174 175 #ifdef CONFIG_SYS_DPAA_PME 176 #ifndef CONFIG_PME_PLAT_CLK_DIV 177 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 178 case 1: 179 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 180 break; 181 case 2: 182 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 183 break; 184 case 3: 185 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 186 break; 187 case 4: 188 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 189 break; 190 case 6: 191 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 192 break; 193 case 7: 194 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 195 break; 196 default: 197 printf("Error: Unknown PME clock select!\n"); 198 case 0: 199 sys_info->freq_pme = sys_info->freq_systembus / 2; 200 break; 201 202 } 203 #else 204 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 205 206 #endif 207 #endif 208 209 #ifdef CONFIG_SYS_DPAA_QBMAN 210 sys_info->freq_qman = sys_info->freq_systembus / 2; 211 #endif 212 213 #ifdef CONFIG_SYS_DPAA_FMAN 214 #ifndef CONFIG_FM_PLAT_CLK_DIV 215 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 216 case 1: 217 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 218 break; 219 case 2: 220 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 221 break; 222 case 3: 223 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 224 break; 225 case 4: 226 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 227 break; 228 case 5: 229 sys_info->freq_fman[0] = sys_info->freq_systembus; 230 break; 231 case 6: 232 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 233 break; 234 case 7: 235 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 236 break; 237 default: 238 printf("Error: Unknown FMan1 clock select!\n"); 239 case 0: 240 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 241 break; 242 } 243 #if (CONFIG_SYS_NUM_FMAN) == 2 244 #ifdef CONFIG_SYS_FM2_CLK 245 #define FM2_CLK_SEL 0x00000038 246 #define FM2_CLK_SHIFT 3 247 rcw_tmp = in_be32(&gur->rcwsr[15]); 248 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 249 case 1: 250 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 251 break; 252 case 2: 253 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 254 break; 255 case 3: 256 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 257 break; 258 case 4: 259 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 260 break; 261 case 5: 262 sys_info->freq_fman[1] = sys_info->freq_systembus; 263 break; 264 case 6: 265 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 266 break; 267 case 7: 268 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 269 break; 270 default: 271 printf("Error: Unknown FMan2 clock select!\n"); 272 case 0: 273 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 274 break; 275 } 276 #endif 277 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 278 #else 279 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 280 #endif 281 #endif 282 283 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 284 285 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 286 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 287 & 0xf; 288 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 289 290 sys_info->freq_processor[cpu] = 291 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 292 } 293 #define PME_CLK_SEL 0x80000000 294 #define FM1_CLK_SEL 0x40000000 295 #define FM2_CLK_SEL 0x20000000 296 #define HWA_ASYNC_DIV 0x04000000 297 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 298 #define HWA_CC_PLL 1 299 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 300 #define HWA_CC_PLL 2 301 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 302 #define HWA_CC_PLL 2 303 #else 304 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 305 #endif 306 rcw_tmp = in_be32(&gur->rcwsr[7]); 307 308 #ifdef CONFIG_SYS_DPAA_PME 309 if (rcw_tmp & PME_CLK_SEL) { 310 if (rcw_tmp & HWA_ASYNC_DIV) 311 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 312 else 313 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 314 } else { 315 sys_info->freq_pme = sys_info->freq_systembus / 2; 316 } 317 #endif 318 319 #ifdef CONFIG_SYS_DPAA_FMAN 320 if (rcw_tmp & FM1_CLK_SEL) { 321 if (rcw_tmp & HWA_ASYNC_DIV) 322 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 323 else 324 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 325 } else { 326 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 327 } 328 #if (CONFIG_SYS_NUM_FMAN) == 2 329 if (rcw_tmp & FM2_CLK_SEL) { 330 if (rcw_tmp & HWA_ASYNC_DIV) 331 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 332 else 333 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 334 } else { 335 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 336 } 337 #endif 338 #endif 339 340 #ifdef CONFIG_SYS_DPAA_QBMAN 341 sys_info->freq_qman = sys_info->freq_systembus / 2; 342 #endif 343 344 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 345 346 #ifdef CONFIG_U_QE 347 sys_info->freq_qe = sys_info->freq_systembus / 2; 348 #endif 349 350 #else /* CONFIG_FSL_CORENET */ 351 uint plat_ratio, e500_ratio, half_freq_systembus; 352 int i; 353 #ifdef CONFIG_QE 354 __maybe_unused u32 qe_ratio; 355 #endif 356 357 plat_ratio = (gur->porpllsr) & 0x0000003e; 358 plat_ratio >>= 1; 359 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 360 361 /* Divide before multiply to avoid integer 362 * overflow for processor speeds above 2GHz */ 363 half_freq_systembus = sys_info->freq_systembus/2; 364 for (i = 0; i < cpu_numcores(); i++) { 365 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 366 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 367 } 368 369 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 370 sys_info->freq_ddrbus = sys_info->freq_systembus; 371 372 #ifdef CONFIG_DDR_CLK_FREQ 373 { 374 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 375 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 376 if (ddr_ratio != 0x7) 377 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 378 } 379 #endif 380 381 #ifdef CONFIG_QE 382 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 383 sys_info->freq_qe = sys_info->freq_systembus; 384 #else 385 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 386 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 387 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 388 #endif 389 #endif 390 391 #ifdef CONFIG_SYS_DPAA_FMAN 392 sys_info->freq_fman[0] = sys_info->freq_systembus; 393 #endif 394 395 #endif /* CONFIG_FSL_CORENET */ 396 397 #if defined(CONFIG_FSL_LBC) 398 uint lcrr_div; 399 #if defined(CONFIG_SYS_LBC_LCRR) 400 /* We will program LCRR to this value later */ 401 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 402 #else 403 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 404 #endif 405 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 406 #if defined(CONFIG_FSL_CORENET) 407 /* If this is corenet based SoC, bit-representation 408 * for four times the clock divider values. 409 */ 410 lcrr_div *= 4; 411 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 412 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 413 /* 414 * Yes, the entire PQ38 family use the same 415 * bit-representation for twice the clock divider values. 416 */ 417 lcrr_div *= 2; 418 #endif 419 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 420 } else { 421 /* In case anyone cares what the unknown value is */ 422 sys_info->freq_localbus = lcrr_div; 423 } 424 #endif 425 426 #if defined(CONFIG_FSL_IFC) 427 ccr = in_be32(&ifc_regs->ifc_ccr); 428 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 429 430 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 431 #endif 432 } 433 434 435 int get_clocks (void) 436 { 437 sys_info_t sys_info; 438 #ifdef CONFIG_MPC8544 439 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 440 #endif 441 #if defined(CONFIG_CPM2) 442 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 443 uint sccr, dfbrg; 444 445 /* set VCO = 4 * BRG */ 446 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 447 sccr = cpm->im_cpm_intctl.sccr; 448 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 449 #endif 450 get_sys_info (&sys_info); 451 gd->cpu_clk = sys_info.freq_processor[0]; 452 gd->bus_clk = sys_info.freq_systembus; 453 gd->mem_clk = sys_info.freq_ddrbus; 454 gd->arch.lbc_clk = sys_info.freq_localbus; 455 456 #ifdef CONFIG_QE 457 gd->arch.qe_clk = sys_info.freq_qe; 458 gd->arch.brg_clk = gd->arch.qe_clk / 2; 459 #endif 460 /* 461 * The base clock for I2C depends on the actual SOC. Unfortunately, 462 * there is no pattern that can be used to determine the frequency, so 463 * the only choice is to look up the actual SOC number and use the value 464 * for that SOC. This information is taken from application note 465 * AN2919. 466 */ 467 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 468 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 469 defined(CONFIG_P1022) 470 gd->arch.i2c1_clk = sys_info.freq_systembus; 471 #elif defined(CONFIG_MPC8544) 472 /* 473 * On the 8544, the I2C clock is the same as the SEC clock. This can be 474 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 475 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 476 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 477 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 478 */ 479 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 480 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 481 else 482 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 483 #else 484 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 485 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 486 #endif 487 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 488 489 #if defined(CONFIG_FSL_ESDHC) 490 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 491 defined(CONFIG_P1014) 492 gd->arch.sdhc_clk = gd->bus_clk; 493 #else 494 gd->arch.sdhc_clk = gd->bus_clk / 2; 495 #endif 496 #endif /* defined(CONFIG_FSL_ESDHC) */ 497 498 #if defined(CONFIG_CPM2) 499 gd->arch.vco_out = 2*sys_info.freq_systembus; 500 gd->arch.cpm_clk = gd->arch.vco_out / 2; 501 gd->arch.scc_clk = gd->arch.vco_out / 4; 502 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 503 #endif 504 505 if(gd->cpu_clk != 0) return (0); 506 else return (1); 507 } 508 509 510 /******************************************** 511 * get_bus_freq 512 * return system bus freq in Hz 513 *********************************************/ 514 ulong get_bus_freq (ulong dummy) 515 { 516 return gd->bus_clk; 517 } 518 519 /******************************************** 520 * get_ddr_freq 521 * return ddr bus freq in Hz 522 *********************************************/ 523 ulong get_ddr_freq (ulong dummy) 524 { 525 return gd->mem_clk; 526 } 527